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How do you size PCB traces when you have both high-speed and high-current requirements?
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2
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14
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June 3, 2026
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How do you validate and optimize RF PCB performance after layout?
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2
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22
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May 27, 2026
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How do you validate high-speed PCB performance after layout?
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2
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33
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April 29, 2026
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CAN Bus PCB Routing – Two Nodes with Unequal Distance to Single Connector
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9
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78
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April 18, 2026
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Trace under the passive components is allowed? is any IPC standard specify this point
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1
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63
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November 21, 2025
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Webinar: Characterization of High-Frequency Transmission Lines for Signal Integrity optimization
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0
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825
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November 12, 2025
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PCB designer is asking for some of the math behind "the signal is in the field"
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7
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266
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September 26, 2025
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Webinar: Practical Techniques for Ensuring Power Integrity in High-Speed Designs
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3
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807
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September 2, 2025
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Non-symmetric Stackup
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6
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309
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August 12, 2025
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The 4 problems that degrade your high-speed serial links by Prof. Eric Bogatin
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0
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61
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July 22, 2025
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DDR3 Interface Design with STM32MP157FAC1 Using KiCad
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1
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250
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July 3, 2025
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How to Design a PCB Trace Antenna with Limited Datasheet Info?
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1
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98
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May 29, 2025
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What is material to be use for PCIe Gen 6.0/7.0?
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5
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236
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May 28, 2025
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Clarifying my understanding of the 8-layer PCB stack up focusing on DDR3, PMIC sequencing, and ground/power plane design
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4
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364
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May 22, 2025
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Webinar: Resolving High-Speed PCB Design Challenges
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1
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188
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May 21, 2025
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DDR3 Address/Command/Clock Length Matching Clarification – Is My Understanding Correct?
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3
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326
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May 13, 2025
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Clarifying My Understanding of DDR3 Signal Routing
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8
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512
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May 8, 2025
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Routing of high-speed signals (DDR, USB) on outer layer
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2
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139
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May 7, 2025
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How to Length Match RGMII Data Lines — Meanders Not Forming on Shortest Trace in KiCad
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6
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265
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April 29, 2025
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How to implement 1.5–2.0ns delay in RGMII TXC trace for RTL8211F?
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6
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409
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April 28, 2025
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Webinar: Design Strategies for Minimizing Jitter and Insertion Loss in High-Speed PCBs
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1
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664
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January 30, 2025
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How to Use the ‘Tune Differential Pair Skew’ Tool to Match Trace Lengths in kicad?
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4
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561
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January 30, 2025
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Active Antenna RF Design
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13
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419
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January 30, 2025
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"The signal doesn't flow on a conductor."
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0
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36
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January 9, 2025
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Achieving 50 Ohm Impedance and Signal Integrity in 4-Layer PCB RF Design
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4
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337
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January 8, 2025
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Internal layer utilization in a multilayer high-speed design
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2
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89
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November 12, 2024
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Calculating Trace Length Tolerances in High-Speed PCB Design
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3
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1118
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October 18, 2024
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Webinar: High-Speed PCB Design and VNA Testing
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2
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866
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October 16, 2024
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Ask Me Anything with Allan Knox
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10
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623
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September 11, 2024
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Ask Me Anything with PCB West speaker Syed Ubaid Ali Warsi (high speed and EMC)
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13
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717
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March 23, 2024
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