Topics tagged high-speed

Topic	Replies	Views	Activity
Design Considerations for LPDDR4/LPDDR5 Signal Probing Schematic and layout high-speed , via , signal-integrity , pcb-design	2	117	July 30, 2026
How do you size PCB traces when you have both high-speed and high-current requirements? Design and Layout high-speed , high-power	2	186	June 3, 2026
How do you validate and optimize RF PCB performance after layout? Design and Layout emc , high-speed , emi , signal-integrity	2	125	May 27, 2026
How do you validate high-speed PCB performance after layout? Design and Layout high-speed , signal-integrity , vna	2	94	April 29, 2026
CAN Bus PCB Routing – Two Nodes with Unequal Distance to Single Connector Design and Layout high-speed , signal-integrity , dfm , pcb-design	9	224	April 18, 2026
Trace under the passive components is allowed? is any IPC standard specify this point Design and Layout high-speed , ipc-class-3	1	124	November 21, 2025
Webinar: Characterization of High-Frequency Transmission Lines for Signal Integrity optimization Webinars & Events high-speed , transmission-line , signal-integrity	0	872	November 12, 2025
PCB designer is asking for some of the math behind "the signal is in the field" Schematic and layout high-speed	7	368	September 26, 2025
Webinar: Practical Techniques for Ensuring Power Integrity in High-Speed Designs Webinars & Events high-speed , power-integrity , power	3	857	September 2, 2025
Non-symmetric Stackup Design and Layout high-speed , power-integrity , stackup , stack-up , signal-integrity	6	384	August 12, 2025
The 4 problems that degrade your high-speed serial links by Prof. Eric Bogatin High Speed and Frequency high-speed , signal-integrity	0	81	July 22, 2025
DDR3 Interface Design with STM32MP157FAC1 Using KiCad Design and Layout high-speed	1	426	July 3, 2025
How to Design a PCB Trace Antenna with Limited Datasheet Info? Design and Layout high-speed	1	146	May 29, 2025
What is material to be use for PCIe Gen 6.0/7.0? Flex and rigid-flex high-speed	5	363	May 28, 2025
Clarifying my understanding of the 8-layer PCB stack up focusing on DDR3, PMIC sequencing, and ground/power plane design Design and Layout high-speed	4	491	May 22, 2025
Webinar: Resolving High-Speed PCB Design Challenges Webinars & Events high-speed , pcb-design	1	207	May 21, 2025
DDR3 Address/Command/Clock Length Matching Clarification – Is My Understanding Correct? Design and Layout high-speed	3	467	May 13, 2025
Clarifying My Understanding of DDR3 Signal Routing General high-speed	8	697	May 8, 2025
Routing of high-speed signals (DDR, USB) on outer layer Design and Layout high-speed	2	203	May 7, 2025
How to Length Match RGMII Data Lines — Meanders Not Forming on Shortest Trace in KiCad Tutorials and demos high-speed	6	383	April 29, 2025
How to implement 1.5–2.0ns delay in RGMII TXC trace for RTL8211F? Design and Layout high-speed	6	608	April 28, 2025
Webinar: Design Strategies for Minimizing Jitter and Insertion Loss in High-Speed PCBs Webinars & Events high-speed , jitter , insertion-loss	1	708	January 30, 2025
How to Use the ‘Tune Differential Pair Skew’ Tool to Match Trace Lengths in kicad? Tutorials and demos high-speed	4	763	January 30, 2025
Active Antenna RF Design Design and Layout high-speed	13	533	January 30, 2025
"The signal doesn't flow on a conductor." Signal and Power high-speed , signal-integrity , rick-hartley , trace-talks	0	46	January 9, 2025
Achieving 50 Ohm Impedance and Signal Integrity in 4-Layer PCB RF Design Design and Layout high-speed , signal-integrity	4	429	January 8, 2025
Internal layer utilization in a multilayer high-speed design Design and Layout high-speed	2	144	November 12, 2024
Calculating Trace Length Tolerances in High-Speed PCB Design Design and Layout high-speed , signal-integrity	3	1338	October 18, 2024
Webinar: High-Speed PCB Design and VNA Testing Webinars & Events high-speed , vna	2	891	October 16, 2024
Ask Me Anything with Allan Knox Ask Me Anything high-speed , ask-me-anything , ama	10	722	September 11, 2024