Internal layer utilization in a multilayer high-speed design

Design and Layout
1

I’m seeking guidance on managing single-ended signals a high-speed 4-layer PCB with Top Layer: Single-ended/TTL signals, Internal Layer 1: Power Plane (3.3V), Internal Layer 2: Ground Plane and Bottom Layer: LVDS signals.

I’ve routed most of my single-ended connections on the top layer, but due to fixed mechanical constraints, I can’t fit all of them there. I’m considering moving some of these traces to the second layer (where the 3.3V power plane is), but I’m concerned this might compromise the power plane’s integrity.

My aim with the internal planes is to isolate the single-ended signals from the differential LVDS traces, especially since the ground plane next to the LVDS traces will remain unbroken. Given this setup, would moving some single-ended traces onto the power plane layer be likely to cause any signal integrity issues?

2

I would say problems come if signals share the return path. This should be the first point to check. Because there is a plane in between, check if the copper plane is thick enough.
Other option could be modify the stack-layer:
Ground/signal+PWR/signal/Ground.
Now you don´t have signals on the top layer. In a typical 4 layers PCB there is a big distance between layer 2 and 3 because (the core is in between) compare to the distance between layer 1 and 2 . So most probably no crosstalk between LVDS and single-ended signals. You have to check it.

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3

If your high-speed signals are all LVDS, then using the top layer for signal breakout should work well, provided single-ended signals don’t cut through the critical areas of the plane. If you have space on the bottom layer, this may be a better choice for additional single-ended traces, allowing the power plane layer to stay uninterrupted. Ensure proper spacing rules for isolation.

However, there’s generally no issue using a power plane layer for a few single-ended signals, as long as the number of traces is limited to maintain copper balance. Your PCB manufacturer can offer guidance on this for optimal stability. Prioritize the plane layer for high-speed signals, especially if LVDS traces are on the bottom with a solid ground reference. This setup minimizes potential signal integrity issues since LVDS signals would remain grounded as intended.

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