Routing LVDS Channel Above Power Plane

I’m currently working on a 4-layer PCB design featuring 16 channels of LVDS (differential signaling, 480MHz). My layer stack-up follows the order of Signal-GND-Power-Signal. Typically, a microstrip design for LVDS channels involves traces over a ground plane. However, I’m exploring the possibility of implementing controlled impedance differential pairs on the other signal layer, where the adjacent copper plane is not ground but a power plane (specifically 3.3V).

I’m curious if running some LVDS channels above this power plane is feasible. Then, on the subsequent connector that links these LVDS channels to another board, the connector would be referenced to ground (with ground lines distributed throughout the cable to minimize ground loops) instead of the power rail.

Any advice on the feasibility and potential considerations of this setup would be greatly appreciated.

A power plane is often used as a reference plane as well. There are some minor degradations in performance but if you need to do it that way it should work, particularly if the ones using ground as a reference are different groups than the ones using Vcc.

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Yes, it certainly is possible. You can achieve this by placing decoupling capacitors between two planes, especially near the points where the LVDS signals transition from one side to another. It provides a pathway for the AC return current to move from one plane to another.
While LVDS signals primarily carry the AC return current on the opposite side of the differential pair, a portion still flows through the power or ground plane. LVDS signals are generally well-balanced, but there might be some imbalance. The less balanced they are, the more return current flows on the power/ground plane.

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In addition to the above points, I suggest maintaining continuity in signal routing on a single plane whenever feasible. Even if signals need to transition to another plane, strive to keep them on the same plane for as long as possible. If necessary, use vias to connect to the other chip pins, ensuring proper termination at that point with dedicated vias.

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