Signal Return Paths in a multilayer PCB Stack-Up

I am considering the following 6-layer stack-up for a mixed-signal board and would appreciate feedback:

Layer 1: Top (Analog signals & components)
Layer 2: GND
Layer 3: PWR (Supply 1, Supply 2, Supply 3)
Layer 4: SIG (High-speed digital signals)
Layer 5: GND Layer
6: Bottom (Control signals)

Layers 2 and 5 are solid ground planes with no splits in the copper. Layer 3, the power plane, is divided into several regions (AVDD, DVDD, VCLK).

My objective is to maintain a clean ground on layer 2. I assume that the high-speed return current should flow through Layer 5. Since this plane is directly underneath the high-speed signal trace, it should provide the lowest impedance return path. Is this assumption correct? Does this stack-up configuration make sense?

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I think “High-Speed digital signals” should be on layer 1. First of all if the high speed signals are distributed on layer 4 you need VIAS´s from layer 1 to layer 4 and the other way around from layer 4 to layer 1. Every time a VIA is on the High Speed digital signal path the signal is distorted. If it is possible, VIA´s should be eliminated if you are working with High Speed digital signals.

On the other side signal on layer 4 is some kind of strip line because there are two return paths, one on the bottom (GND) and one on the top (supply 1, supply 2, supply 3). The first return path will have some continuity through the GND plane but the second one no because this plane is split. Even more, the return path has to be a GND plane if you use power planes the final impedance will be the impedance between the signal and power plane plus the impedance between the power plane and GND. You have to evaluate the second term.

Move layer 4 to top layer.


If top layer are all components, I would recommend routing high speed signals on top layer and layer 3 if needed. L2 will be common return path to both top and L3 (minimizes needing high speed return path vias since using common layer for return path).

If analog components are also on top layer, they should be physically isolated from the digital areas as much as possible. Analog signals likely will be more forgiving if they need to transition to the far side of the stackup.


Thanks @eduardo.mateos and @timothy.phillips!

@Criniveran1988 you can also read this blog on How to Build a Multilayer PCB Stack-up for more info.

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I see, thanks for the advice.

Got it, thanks. I will try.

The advice already given makes sense, though it does not infer that your present stack-up won’t work. In the end it comes down to the details, and that’s difficult in a forum like this.

For example, what do you mean by high-speed digital signals? If you are thinking about say I2S interfaces that operate at a few MHz and have rise/fall times of the order of a few ns, it is not difficult to make layer transitions look transparent. If that’s the case, then changing between layers is not a problem if it is done correctly. But if the interface you have in mind is say USB2 with a fundamental frequency of around 250 MHz, and certainly if it is USB3 with a fundamental frequency of 2.5GHz (and their respective rise/fall times), getting the layer change to look transparent becomes much harder. From this we can use what might be considered a derivative of Lord Falkland’s rule changed to apply to signal integrity: if it is not necessary to make a layer change, it is necessary not to make a layer change. Things like this drive the bits that are hard to do well, and may require the high-speed digital signals to be on layer 1.

Another concern has been raised about the impact of the high-speed digital signals being on layer 4 having two reference planes (layers 3 and 5) of which one is a split plane. Does this matter? The answer is “it depends”.

To explain the above a bit better, let’s start with a generalisation: splitting GND planes is not a good plan 99+% of the time. And now a recommendation: reference all signals to GND and not to PWR because the GND planes are not split. The benefit of the recommendation is that when you have multiple GND layers and a signal layer transition makes the new signal layer reference a different GND plane, all you have to do to link them together is put a GND via next to your signal via. In the case where you have signals adjacent to a PWR plane, and they cross to anything else, you must link the reference path with a capacitor but this is a much inferior solution (and is usually rubbish above 50MHz or so).

From this it looks like the solution is to use capacitors to link the different supplies on the PWR layer, thus giving a poor approximation of a continuous plane (poor, but better than nothing). The question is whether it is necessary? At this point, we need numbers to see what’s happening.

The original post that started this thread only tells us part of the story. Of the things that are missing, we do not know the separations between the layers. Let’s start filling in some assumptions. Let’s make layer 1 to layer 2 be 50um. This makes it easy with FR4 to get sensible track and gap widths to make 50 Ohms single-ended and 90/100 Ohms differential impedances and being very thin, it maximises the coupling between signal and GND. The GND to PWR separation also works best if this is thin, again, let’s say 50um. Since capacitance is inversely proportional to distance, this maximises the buried capacitance between GND and PWR, which is great because it comes for free and will out-perform the capacitors on the board above 50MHz. If we assume 0.5oz copper (18um) then the thickness of this is 18 * 3 + 50 * 2 = 154um. The other three layers are symmetric, thus we have accounted for about 300um of board thickness. If we want the PCB to be 1.6mm (1600um), then the separation between layer 3 (PWR) and layer 4 (sig) is about 1300um. It follows that the influence of layer 5 (GND) dominates as it is 26x closer to the signals on layer 4 than layer 3 is. In practice, the plane splits on layer 3 are effectively unimportant. Note that this would not be true if the PWR plane was much closer. This highlights the importance of fully defining the stack-up, and not leaving it up to the PCB supplier to choose.

Reading between the lines, it looks as though the idea for the GND planes is to have one be a quiet GND (layer 2) and the other be a noisy GND (layer 5). This is a subtle way of introducing a GND plane split by splitting it vertically. Of course, if you have any signals on layer 1 that must transition to layers 4 or 6, you will need a GND stitching via next to the signal via, which undoes the idea of separated planes.

Do planes become noisy because of having high-speed digital signals routed close to them? No. The high-frequency signals induce displacement currents in the immediate vicinity of the signal path. The closer they are together, the more tightly defined the displacement current path is as it follows the signal path. This is not significantly interfering with anything. Just keeping the analog signals away from the digital ones (to minimise crosstalk) covers most things. How far away? 3x layer separation between signal layer and the reference plane is a good start, 5x separation is better, but beyond this there is little to be gained. Once more, the key is that the closer you can make the layers, the better. Therefore, don’t think analog GND is quiet and digital GND is noisy, because this is usually not the case unless the design is put together without thought of where each return path is.

Now to the original question - does the stack-up make sense? Answer, it could. If the frequency / edge rates for the digital part are fast, they drive the design, and minimising layer changes is the best plan. After that, it is better to treat GND as being the same everywhere and in addition to stitching the GND planes together where you have signal transitions, put in a grid of GND stitching vias that are between 5-10mm apart. Last, choose the layer spacings to best meet the needs of your planned layer usage. This has been covered above.

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Thank you, Jonathan, for your detailed and insightful answer. Your advice has been extremely helpful in understanding the complexities of my stack-up and high-speed signal management. I appreciate the time you took to provide such a thorough explanation. This will certainly help me refine my stack-up design to ensure optimal performance. Thanks again for your valuable input!

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In this design, the return current for high-speed digital signals on layer 4 will be approximately evenly split between layers 3 and 5. This arrangement works well as long as layer 3 is free from discontinuities (isolation gaps) along any digital lines. Careful routing can help achieve this. This way, planes 1 and 2 remain unaffected by digital signals.
However, if avoiding gaps in layer 3 across the digital lines isn’t possible, you’ll need to route these signals on the bottom layer instead.

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