Effective 4-Layer PCB Stack-Up Strategies for high density boards

Design and Layout
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I need advice on designing a stack-up for a 4-layer PCB with a high-density top layer. I understand that the optimal stack-up configurations are usually either Option 1 or Option 2 because they provide a good return path.

Column 1 Column 2 Column 3
Option-1 Option-2 Option-3
SIG/PWR GND SIG
GND SIG/PWR GND
GND SIG/PWR PWR
SIG/PWR GND SIG

Option 1: I can’t route power or create a power pour on the top layer because it’s packed with components and signal traces, and expanding the PCB isn’t possible.
Option 2: The GND plane would be excessively fragmented due to the components.
Would it be acceptable to use a option 3 stack-up if I place a return via (connected to GND) next to each via connecting the top and bottom signals? Although there won’t be many vias connecting the top and bottom layers, the bottom layer is mostly empty and needs to stay that way.
For context, this is a low-speed DC circuit, so I could probably get away with using a standard stack-up, but I’m aiming to develop best practices for reducing EMI.

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Absolutely! I would use the third option myself. And for a four layer board I’d probably consider that my default.

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This is a good question because all options have pros and cons. Option 3 sets the core between GND and PWR, so it means there will be a big distance between both planes and the capacitance will be small. This is not the optimal situation. Rick Hartley recommends the option 2 (see videos) but there are also some drawbacks. There is crosstalk between layers 2 and 3 and on the other site as you need many VIAS to route on the internal layers, the more VIAS´s the more difficult to route. My favorite is number 1. The reason is because is the best option if you need to use VIAS´s between both signal layers. Doing like this there is continuity in the return path (all the internal layers are connected to GND). I would say this is the best option in case a high data rate is included.
Honestly if it is a low speed circuit I think you shouldn´t have any problem if you use Option 3.

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For almost all commercial designs, the option-3 stack-up is more than adequate—it’s the industry standard for a reason!

Regarding stitching planes: when you use bypass capacitors with vias near signal vias, you don’t need to worry too much about stitching. The wide area and close coupling of the planes take care of this for you. A few bypass capacitors placed strategically should be sufficient, and you probably already have enough from the local bypasses at the chips.

If you find you need more routing area, consider moving to a six-layer board. You can maintain the VCC/GND on Mid1 and Mid4, adding two extra routing layers or additional planes as needed. You can also route within the planes if you have room for stitching vias.

This general scheme—reserving about half of all layers for planes while respecting symmetry—applies to any number of layers. For example, PC motherboards often use 8 layers, while server backplanes and other specialized equipment can use 32 or more layers, with nearly every other layer as a plane.

On a six-layer board, you shouldn’t have three planes placed symmetrically. Boards are laminated in layer or core pairs, so you should use symmetrical dielectric and copper layers. For a six-layer board, it’s best to use two or four planes to maintain a balanced build.

Unbalanced copper density can lead to warpage as the freshly bonded PCB cools down, causing mechanical problems and poor soldering on dense SMT components. This issue mainly affects large boards (300mm+) or when there are significant density mismatches (like nearly empty layers vs. solid planes). As long as you make modest use of all layers and the board isn’t too large, you shouldn’t worry much about it.

When you need exceptional performance (such as in military or aerospace applications), you might need to prioritize performance over ease of layout and manufacturing. In these cases, an internal-based design with many GND planes and additional power-routing layers can be beneficial. However, sometimes the benefits of such layouts might not be significant enough (e.g., when you need 80dB+ shielding but only achieve 10-30dB with layout tricks), and a shield can might still be required. Often, a shield can be cheaper than adding extra board layers.

Ultimately, it’s about choosing the right option for your needs. Explore different approaches and see what works best for your project, considering budget and time constraints.

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There is chatter that GND planes on the outside provide EMI shielding. We have a word for this - WRONG. All currents (i.e. signals) have return currents, usually on the lowest-possible impedance path - hopefully the ground plane. Unless your outer plane is NOT used for signal ground, it will not be a shield. EMI does not come from currents on the surface - it comes from OPEN LOOPS - which happens when the return current has to follow paths far from the original signal path. A close GND OR PWR plane provide a good return path (they are closely coupled together through low-impedance paths i.e. caps). The close proximity of the plane on which ever side the signal is on is what keeps the loops small and tight, and keeps EMI down. Hence why I, and many other professionals, only use Option 3.

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Oh, and the capacitance provided by placing GND and PWR close together is negligible for most applications. A single 0.1uF ceramic cap will provide more than the planes.

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So option 3 it is! :smiley: thanks everyone for your advice.

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This is probably a bit late in the day for comments, but as one question doesn’t seem to have been answered, a late reply isn’t entirely out of place.

Option 1 is the only solution that makes EMC easy if you follow simple rules. As has already been said, option 2 can also work, but densely packed boards make this approach pointless (this is down to the fact that most people forget the rule that says you must not pass signals over splits in GND planes - and thus few implement option 2 as it is meant to be done). Option 3 can work but is very difficult to make it really quiet from an EMC point of view. Bottom line is that if you want EMC to be easy, it has to be option 1.

The question raised that appears to have been missed is whether putting GND vias at signal transition points while implementing option 3 gives any benefits.

Suppose for now that these GND vias are just that. In other words they are simply there and do not connect anything together, they are simply posts sticking up through the GND plane. These vias give you no benefits whatsoever. They are a total waste of space. The reason for this is that the top layer signals induce displacement currents in the adjacent GND layer. When a transition between top layer and bottom layer takes place, the displacement current is now being formed in the PWR layer. How does it connect through to the GND layer to complete the circuit? Answer, it can’t. The GND to PWR impedance is very high, so the current cannot make the transition and instead it spreads out across the board and now being unlinked to the original tracks, it radiates badly. (Now you see why two GND layers makes a lot of sense; a GND via next to the signal via allows the displacement current to change layer very easily - thus no radiation).

The other scenario is that the GND via is next to a PWR via and on the component layer you have a capacitor linking the two vias together. The capacitors allow the displacement current through (it is AC anyway) and this sounds like it should work, but the problem is that the AC impedance of the capacitors are dominated by the capacitance only at low frequencies (typically about20-30MHz) and look inductive above this frequency. This is unfortunate since the frequency range 30MHz-1GHz is a radiated emissions hot-spot, and the capacitors are not doing much to keep this noise down.

In the initial description, it was stated that this is a “low-speed DC” circuit, which is probably the only use case for Option 3. The issue is how low is low enough to not have to worry about going down this route?

Since the top side component density is high, and thus put forward as the reason for not routing power on that layer; but the bottom layer is stated as being kept as empty as possible, the obvious question is why not route all the power on the bottom layer. Doing this means the inner PWR plane is not required and can be turned into a second GND plane. Now all you need is a GND stitching via (or two) next to each signal transistion and you have the best solution.

If you want to see simulations of signal layer transitions with different numbers of GND stitching vias (or none), have a look at the Simbeor website and find their apps notes and papers page (SIMBEOR® Electromagnetic Signal Integrity Software) and look at the videos they have made and you will see why GND stitching vias are important. In the same place you will also see videos that show what happens when a signal crosses a split in a plane, and where the energy actually goes (as this is the prime reason why option 2 is almost always done wrongly).

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The considerations I’m outlining here are primarily for high-speed circuits. They may not be necessary for DC circuits, but since the question is about the best practices, I’ll provide a general overview.

The stack-ups in options (1) and (2) would work, but not option (3). In the option (3) stack-up, signals on the bottom layer are referenced to a ground plane, and those on the top layer are referenced to the power plane. You can’t simply use a stitching via connected to the GND plane, as it would create a dead short between the power and ground planes. To provide a high-frequency return path, you would need to connect the stitching via to the GND plane and use a capacitor to connect it to the power plane.

However, this approach would require a lot of capacitors. That’s why modern high-speed designs typically avoid using power planes as reference planes. With increasing speeds and decreasing PCB layer costs, opting for dedicated ground planes is generally more efficient.

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Hi Tracy. You are right, the capacitance between Vcc plane and the return plane (GND) is almost negligible. On the other side it is a very good quality capacitor. In any case the reason why VCC and GND should be as close as possible (2 or three mils no more) is not because capacitance, it is because inductance. Keep the distance between the signal or Vcc and the return path as closer as possible and the inductance loop will drop.
Regarding the best stack up in terms of EMI/EMC you can see a very good webinar “PCB Design for low EMI” Kenneth Wyatts (for free in this webpage). I do recommend it.

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