Optimal Placement of Stitching Vias

Hello, I’m implementing a 4-layer stackup for my SMPS design (approximately 100 W) structured as follows: Signal-GND-GND-Power. I’ve come across information suggesting that the inductance of stitching vias might adversely affect the switching nodes, so it’s advised to avoid them. However, should I still consider placing stitching vias in void areas away from switching nodes? If yes, should these vias require a ground pour in the top and bottom plane, or can they be placed without it?

I would use the stitching vias. First carefully check the mfg. data sheet for the switching IC. I would also use the ground pours (and power) because generally speaking, the ore copper the better.

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Stitching vias are primarily utilized for managing high-frequency signals effectively. Incorporate lots of ground vias, but carefully consider their placement. Pay close attention to the recommendations provided by chip manufacturers, especially when dealing with sensitive components like switchers that are prone to noise interference.

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Having adjacent ground planes can result in inefficient use of PCB real estate. A more optimal approach would be to consider a stack-up with signal+Vcc, GND, Vcc, signal+GND layers, and implement via stitching between them.

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What is the reason to put Power on the bottom, rather than sandwiching it between the grounds?

I assumed this would be the way to optimize the stackup. No? @JimJJewett

@saitter I am not an expert, but my understanding was that you should put ground near your signal traces, and then near your power traces, and then near your power planes, and then on the outside as shielding.

I suppose the biggest interaction of your power plane will be with the adjacent ground plane regardless of which order the bottom two are in. It just seems like the extra capacitance (and load cushioning) with your other ground plane also has value, as does the shielding, and I don’t see what you’re getting in return by having two grounds next to each other.

I understand the suggestion from @myrtlee
I would also understand going to a 2-layer board to save costs, or putting a pair of grounds in the middle and routing power along traces instead of reserving any power plane. But I don’t see why you want a power plane on the outside.

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It may be a bit late to add to this thread, but there are a few things that perhaps should be said.

PCB stackup:
the original suggestion was the best one: Sig-GND-GND-Pwr. This works best when the Sig-GND is separated by a thin core (0.05mm to 0.1mm but closer is better), and GND-Pwr will have to match this, for reasons of symmetry. This means that for those times when you have to run signals through part of the Pwr layer (or vice-versa) changing layers means changing GND planes, so linking them with vias is much better than the classic (but terrible) putting GND and Pwr on inner layers because now your displacement currents flow on a layer that is a different voltage, so you need decoupling capacitors where the signals change layer.

PSU layout:
Keep it all on the same layer. A mixture of top layer and bottom layer makes things much harder to design well. Don’t route traces under the switching inductor, even shielded inductors will couple into adjacent traces, and the worst signal to route under the inductor is the feedback signal.

Via stitching:
Stitching between the two GND planes is mandatory, in addition to the comments made by others, this is what prevents cavity resonances, but there are places where doing this is not right.
In the switcher itself, it is best to try to route the GND on the same layer as the other main switcher traces (I presume this will be the top layer). This GND area has to be stitched into the two planes, but when the switcher includes the power MOSFETs internally, your choice is already made because most switchers expect the large GND pad under their bodies to be connected through the PCB to help get rid of heat. In this case, adding more stitching vias in different parts of the GND does not help, but makes system noise worse.
So Stitch the GNDs together across the board generally. But don’t stitch through the area where the switchers are, except for the point (usually under the switcher IC) where you link the GND routed as very wide traces on the top layer into the planes.

There was mention in the initial post of whether to put stitching vias in void areas. The answer is yes, and the reason is cavity resonance avoidance. The associated question was whether to add GND copper to make it worth stitching through all four layers. The answer to this is no, they are more likely to cause trouble, and don’t really give you anything much in return. If you’ve got no need to add this extra copper, leave it off; but keep the stitching vias for the reason already given.

Hope that helps.


jonathan.lloyd.riley, do I understand correctly that you like the Signal-GND-GND-Power stackup because you assume a few signals will be routed on not-the-top, and it is better to go to the bottom than to only the third layer? (And that once there, it is better to break up the power plane and reference the alternative GND, than vice versa?)

For the vias, are you saying that, given a ground polygon above a ground plane, and a single connecting ground via, adding a second connecting via makes things worse? (Or maybe just if they’re both near the same source of switching noise?)

For stitching vias in the void areas, is the extra ground pour actually harmful, or just unneeded? I ask because in another question, (@steve.carney ?) mentioned some yield risk from vias with annular rings that don’t connect to anything.

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Concerning 4-layer board stack-ups, there are two good ones that are the best to choose in practically all circumstances. These are Sig-GND-GND-Sig, and the other is GND-Sig-Sig-GND. On both of these, Power is routed on the signal layers. Which of these is best mostly depends on how much you’ve got on the board. Densely populated boards where the GND layers are the outer layers results in GND planes that have a lot of holes in them which constrains where you can route the signal layers (signals crossing holes in the GND planes is bad news), but for boards with low part density, it can give you the option of using vias around the edge of the board and having all the signals in what approximates a Faraday cage. Most of my 4-layer boards tend to be too dense for this to be a good practice, so I prefer to have GND planes with more copper; hence Sig-GND-GND-Sig is my first choice for a 4-layer stack-up.

For now, let’s look a little more closely at Sig-GND-GND-Sig and think about what we need to really make it work for us. All of the signal traces will have an impedance, and the next nearest copper in the stack-up has the dominant effect in working out what that impedance will be. In many cases it may not matter what the figure is, but if you have USB on there, you’ll want the diff-pairs to be 90 Ohms, Ethernet and you want 100 Ohms, many RF traces will want 50 Ohms (single-ended). To make this work you need the GND planes to be very close to the signals to give you signal trace widths that are sufficiently narrow for you to be able to route your board. Now what about power? If you have routed power on the signal layers, and you’ve put copper pours over them to lower the resistance, you’ve now created a capacitor between the pours and the GND plane. This is great because it comes for free and is the only capacitance you’ll have on the board that really works well above 250-500 MHz or so, right up into the GHz arena (which is what you need for the fast switching edges of many high-speed devices these days. How can we maximise the benefit we gain from this? Reduce the separation between signal layer and GND plane. For once, both of these factors are working the same way, we want the Sig-GND separation to be something like 75um to be “good”, or <=50um to be “great”.

How does this compare with Sig-GND-PWR-Sig? Controlled impedance traces for USB/Ethernet/etc. compels Sig-GND to be small (75um). By symmetry PWR-Sig will be the same, but a typical 1600um PCB will now have around 1400um between GND-PWR. You lose about 95% of your buried capacitance, compared to 75um. In the EMC lab, that’s going to hurt. On the other hand, past experience at the EMC lab with a Sig-GND-GND-Sig stack-up and a board with Gigabit Ethernet, USB3 (4 chans), HDMI, multicore CPU running at 1.5 GHz and associated DDR4 memory (and more IO) and the EMC Lab engineer asks “is it on yet?”.

In the initial part of the thread the question concerned a 100W PSU. For this I would imagine having a layer dedicated to getting power in and out of the switchers would be useful. If the majority of parts are on the top side, then the best change to Sig-GND-GND-Sig is to make the bottom layer be power distribution, hence Sig-GND-GND-Pwr. There may need to be some copper weight balancing on the Sig layer for it to be easily manufacturable, but what this is and how it is implemented is getting too specific. It may be that if there are other things on the board other than the 100W PSU, then I would anticipate that once away from the regulators, the Sig-GND-GND-Sig structure with routed power dominates, and now there may well be a lot of signals that change between top and bottom layers, and so having GND as the reference plane in both routing layers makes it extremely easy to link the displacement current paths just by adding vias next to the signal vias.

Now for the first via question. The context here is the routing of GND in a switching power supply, where GND is routed on the same layer as the components (top layer). Here you have significant currents flowing in these GND traces on the top layer. These need to be coupled into the GND planes. Doing this at one place is generally the best approach, and that usually works out to having not one but usually quite a lot of tiny vias right under the switching regulator. The benefit of this is that it reduces noise injection into the GND planes. If you think of a standard buck converter, and think where the “hot loop” is (i.e. from the input capacitor, through the switcher, through the inductor, through the output capacitor, and through the GND trace that links the GND of the output capacitor to the GND of the input capacitor, thus one complete loop). Now consider that there is a changing current level flowing through that loop. A real loop has resistance, and so you must have an IR drop between the two capacitor GND pins. This means the is a voltage gradient along this trace. If stitched into the GND plane in just one place, that gradient is not seen in the plane. But if you put GND vias close to the input capacitor, and also the output capacitor, you compel this gradient to appear in the planes. This makes your planes noisy. Having 16 tiny vias close together (under the switcher) means the amount of noise injected into the plane is much lower. Hence, adding vias thoughtlessly into this GND area actually harms your system’s EMC performance.

Now the second via question. If you have routed power on the signal layers, and have maximised the buried capacitance that comes for free by using thin or very thin prepregs between Sig and GND layers, there won’t be many GND areas to stitch to on the top and bottom layers. In this case, it is likely that the stitching vias that are linking the two GND planes tightly to each other will be vias passing through the whole stackup, but on the top and bottom layers they may come to the surface in a pour placed over a power trace, or just into an area with no copper. Either way, this is still just a standard via with the annular ring size that you specified. This is standard PCB technology and presents no yield risk to anything. Admitted, another solution would be buried vias, since the two GND layers are inside the laminate, but this is a totally unnecessary cost adder.

Now let’s take the other case where it comes up into a GND pour on the Sig layers. Let’s also suppose that your PCB design tool has a feature to automatically add stitching vias according to the rules you set. These rules include specifying a grid size for via placement. So you run this feature and now have an array of Stitching vias linking the GND planes. When you then do the GND copper pour on the signal layers, some areas get little islands of copper, but the tool sees that it didn’t touch any GND (via, trace or pad) so it removes that bit because it would be unconnected copper. But what about the time when there was just one GND via and nothing else was GND, the tool sees that the GND pour is linked to a GND via and so it keeps this GND pour. The difficulty in this case is that you have created an antenna. The worst of these tend to occur close to the board edge where you didn’t need the space to route any signals. So let’s suppose that you have a thin sliver of a GND pour that is 150mm long, it is connected to GND by that one via which we’ll assume for now is close to one end of this bit of copper. This structure now works as a very good antenna for 500 MHz (plus certain harmonics) but is also not bad at many other frequencies, both lower and higher. So let’s suppose you have something on your board that can excite this, it will radiate that energy giving you more EMC problems to deal with. Letting the PCB tool place these stitching vias and copper pours is fine, but only if you look over your whole board afterwards to make sure that it hasn’t created features that actually harm the EMC performance you would otherwise have got. So yes, stitching vias and pours can be bad, but it is better to do this and check after the tool has finished and either add more vias, or delete some of those copper pours to make sure you’ll get a good board. The one thing you don’t need to worry about is extra annular rings from the added stitching vias.


@jonathan.lloyd.riley Thank you; that was pretty comprehensive.

(1) So the problem isn’t with multiple vias, it is with vias at different extremes of the ground-level instability. But given that the ground level is sloshing around, isn’t the surface ground already radiating? Does spreading it into the larger plane at the cost of a few few mils in the vertical direction actually make things worse?

(2) So what you give up with “extra” surface ground pours is simplicity, because now you have to verify that you haven’t accidentally created an antenna. Is it safe to add ground pours so long as they are large enough for the vias to be stitching instead of solo connections?

@JimJJewett quick answers (1) it depends on context, and (2) mostly, but there are other factors that do have consequences.

(1) if the context is say a switching PSU, and you are looking at what happens when you connect all of your circuit GNDs into the planes as close to the components as you can, this does create voltage gradients between these points, dependent on the current and impedance. This does influence other circuits, though this diminishes with distance.

You can picture this as being a little bit like a see-saw where the length of the see-saw represents the voltage gradient along the path for the GND of the hot-loop of the PSU. Let’s suppose the left end of the see-saw represents the input capacitor GND connection, and the right end of the see-saw is the output capacitor GND connection. When the high-side MOSFET turns on, and current flows out of the input capacitor, the see-saw is being pushed down at the left. This makes sense because the current flows through the inductor and charges the output capacitor, so that side of the see-saw rises. When the high side MOSFET turns off and the low side MOSFET turns on, it almost reverses (the bit that doesn’t quite match is that the current in the input capacitor reverses direction, not because it is part of the “cold loop”, but because the current flowing into the circuit to recharge the input capacitor does this). This means that if the GND connections are all directly into the planes, these gradients must also appear there too, and this means noise in the GND planes. But this is avoidable by routing the high-current GND traces on the top layer, and just linking it into the planes at one point. If reality the GND trace impedance must be higher than that of the plane, so the gradients are steeper, but this does not matter because it still only connects into the planes at one point, so the planes stay quiet.

The vision that comes to mind in saying that the ground level is shoshing around makes one think of say water in a glass, but a better description might be to think of it being like an elastic sheet stretched over the top of a drum because the degree of freedom of movement is constrained. You can press the elastic film and you get a localised deflection, and there will be “ripples” that spread out until the new steady-state with pressure applied settles. If nothing changes now, these gradients are fixed in both size and position.

The problem comes when they’re not fixed but oscillating. In this situation you can excite resonances in the materials, and a similar effect is seen with the planes and the GND pours. If the areas are well linked together (vias) you push the prime resonance upwards in frequency, the closer the links, the higher the frequency; hence the general rule is via to via distance < 10% of the wavelength of the highest frequency you’re bothered about.

So in answer to the question, isn’t the surface GND already radiating, the answer is that it doesn’t have to be doing so if you have taken steps to keep things quiet.

Does spreading into a larger plane on the top or bottom layer make things worse? The answer is that it can do. If all you’re thinking about is purely effects in the GND planes coupling in, then that by itself is not too big a deal. But the outer layers are where your signals are, and if these have been linked from top to bottom through vias, but without regard for the displacement current paths, then you will also launch energy into the cavity between the nearest plane and the outer layer copper. If this energy is at a frequency close to the 1/4 wave resonance of a poorly stitched GND pour on that layer, it will get excited by the EM signal propagating through the dielectric (FR4) and be radiated off that copper. So, yes; it can certainly make things worse.

Fixing this is simple, just add more stitching vias to push up the first frequency at which it becomes an efficient radiator.

(2) Most of this should be self-evident from the above. If you put GND pours on the signal layers, just make sure that the distance between vias in this copper is close enough for the via-to-via resonant frequency to be high enough to be unimportant. The worst case condition is a long copper pour that has no components connecting to it and just one via linking it to a plane, because that will be easy to excite to radiate at a frequency that is well within the range EMC testing is concerned with.


Great information! Thanks a lot!

Thanks Jonathan, for the detailed explanation. This helps clear the concept.