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Welcome to SierraConnect! :wave:
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61
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1452
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January 2, 2024
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PCB Manufacturing Inquiry – 0.15 mm Microvias, Buried Vias and Mech through-hole Vias
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0
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1
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August 19, 2026
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Replacing power trace with a copper pour in dense layouts
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1
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8
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August 19, 2026
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Schematic vs layout: What changes when the board design begins?
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0
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21
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August 18, 2026
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Webinar: Arcs and Sparks - My ESD Journey
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2
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50
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August 17, 2026
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Blind via design and PCB fabrication constraints
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4
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28
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August 17, 2026
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Typical Signal Integrity Issues PCB Designers Should Watch Out For
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0
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19
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August 17, 2026
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What’s the biggest lie in PCB design?
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0
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19
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August 14, 2026
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SPOT THE FLAW: Look beneath the package
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1
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10
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August 14, 2026
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How do you ensure your PCB design is ready for RoHS-compliant manufacturing?
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2
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18
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August 12, 2026
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Rigid-Flex Layer Preference
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3
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21
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August 12, 2026
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The History of Flexible PCBs and Their Modern Application
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0
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6
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August 12, 2026
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COURSE: EMC testing by Karen Burnham
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0
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102
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August 11, 2026
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How many design reviews does your board receive?
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0
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19
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August 10, 2026
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SPOT THE FLAW: This trace is carrying more than just a signal
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2
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96
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August 7, 2026
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PCB designer pet peeves: What annoys you the most?
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0
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23
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August 7, 2026
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How do wave-solderable smd packages survive direct wave contact
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3
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29
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August 7, 2026
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PCB Glossary: Creepage and clearance
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0
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64
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August 6, 2026
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Webinar: How to Strategically Plan EMC-compliant PCB Stack-Ups
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4
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634
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August 5, 2026
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What's your approach to BGA fanout before routing the rest of the board?
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2
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31
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August 5, 2026
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Better DFM tip: Three checks to run before submission
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1
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43
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August 4, 2026
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POLL: At what trace/space do you involve your fabricator?
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0
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9
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August 3, 2026
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Ask Greg: What makes a layout manufacturable?
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0
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18
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August 3, 2026
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SPOT THE FLAW: Something isn't quite... positive
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2
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50
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July 31, 2026
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Can return path discontinuities cause conducted emissions on a 4-Layer PCB?
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4
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44
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July 31, 2026
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Webinar: Practical EMI Reduction Techniques Every PCB Designer Should Know
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0
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266
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July 30, 2026
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Finish the sentence: “It passed DRC, but…”
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0
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16
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July 30, 2026
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Design Considerations for LPDDR4/LPDDR5 Signal Probing
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2
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35
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July 30, 2026
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How do you decide when via stubs need to be removed?
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2
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35
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July 29, 2026
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Steps to generate a stack-up with the Stackup Designer tool
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0
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30
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July 28, 2026
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