For a high-speed PCB design with LPDDR3 RAM, the PCB has a 6-layer stack-up as follows:
SIG
GND
SIG
SIG
VCC
SIG
The area between the SoC and RAM is fully covered by VCC-DRAM in the VCC Plane layer. Assuming all impedance control requirements are met for all layers, consider the following questions:
Is it possible to route tracks on any of the signal layers? Are there differences in referencing tracks to GND or VCC?
Is there a requirement to exclusively reference particular signal groups, such as differential pairs or data groups, to GND (routing only to layers 1 and 3) or to VCC (routing only to layers 4 and 6)?
If there is no difference between referencing to GND or VCC, what is the underlying reason that makes VCC and GND planes behave the same when referencing signals?
At the end of the day the return signal has to be GND plane because you use two power terminals VCC and GND and the current which comes in is the same that comes out. If there is a plane between SIG and GND the impedance the signal sees is the impedance between the signal and VCC + the impedance between VCC and GND. Because you have just one GND plane (layer 2), the impedance between VCC (layer 5) and GND (layer 2) is not negligible. If you want to use VCC as a reference minimize the impedance between VCC and GND as much as possible. If layer 4 were GND then everything would be much better: the impedance between VCC and GND drops and layer 3 would be shielded.
Critical lines (High Speed Lines) should be routed on top layer. Doing like this you can eliminate VIA´s and a lot of problems (ground bounce, reflections, noise…etc.)
Keep in mind that VCC plane is not a must. It can be distributed over different planes. Rick Hartley (a very good SI expert) recommends this stack up for 6 layers:
Ensuring GND and VCC are well-connected by capacitors at both ends of signal lines is crucial in high-speed designs. Ideally, you should minimize instances where return currents switch planes to maintain signal integrity. Regardless of which plane the return current flows through, its main concern is the AC impedance of its path.
Signals on layers 3 and 4 reference both GND and VCC planes. You can adjust core and pre-preg thicknesses to maintain consistent impedance across layers. If needed, vary trace widths between offset stripline (layers 3 and 4) and microstrip (layers 1 and 6) configurations to achieve the desired signal performance.
As to part 7, you can always run tracks on any layer, but for example you wouldn’t want to create open areas on your ground plane. The most common method is probably to run power track around the perimeters of what otherwise would be a signal layer. As to Part 8 I don’t know of any rules covering that. And lastly as to #9, think of it this way - you ground plane layer and your Vcc layer (for example) can be thought of as a voltage source. An ideal voltage source would have zero impedance and therefore act identically to the ground plane as far as references go. The usual problem is that the Vcc plane isn’t an ideal source, and in fact most seem to agree it’s just not nearly as good of a choice as the ground plane. I have to admit I’ve never even thought of using a voltage plane as a return path.
the Rich Hartley recommendation is a mistake due to unbalance copper weight.
the top 3 layers contains 1 full plane of 2 Oz while the bottom 3 layers contains 2 full planes of 2 Oz.
so you may choose your stackup or :
GND/Sognal
Signal
GND
PWR
Signal
GND/Signal
Best Solution for DDR3/DDR4/DDR5 is 8 Layers minimum:
1 Top short Signals & Differential Pairs
2 GND
3 Signal
4 GND
5 PWR
6 Signal
7 GND
8 Bottom short Signals & Differential Pairs