I’m currently designing my first multilayer PCB , which includes a 361-ball TFBGA and a 96-ball DDR3, using HDI fan-out techniques. While going through various stack up design references, I learned that signal layers should ideally be adjacent to ground planes to ensure proper return paths for high-speed signals.
However, when using a stack up design tool, the output didn’t maintain this adjacency, so I planned a stack up structure that better fits the signal integrity needs.
Here is the planned 8-layer stack up (from top to bottom):
layer 1: signal (impedance-controlled, used for DDR3 and PHY)
layer 2: ground (reference for layer 1)
layer 3: signal (impedance-controlled, used for DDR3 and PHY)
layer 4: ground (reference for layer 3)
layer 5: power (includes VDD_DDR and other rails)
layer 6: signal (impedance-controlled, used for DDR3 and PHY)
layer 7: ground (reference for layer 6)
layer 8: signal
I would like to clarify a few things
The DDR3 datasheet mentions that VDD_DDR requires a solid plane without splits. Does this mean the entire layer (like layer 5) should be dedicated only to VDD_DDR, or is it acceptable to include other power rails as long as the VDD_DDR region is kept solid and continuous?
The PMIC I’m using provides sequenced power rails with different ranks (for example, VDD_CORE as rank 1, VDD as rank 2, etc.) to control the power-up sequence. Does the order of power sequencing influence how power planes should be arranged in the stack up? For example, should VDD_CORE be placed closer to the top or bottom layers, or does the physical position of these planes not matter for sequencing?
Is it acceptable to split ground layers, especially the reference ground layer for impedance-controlled traces? What happens if I keep only a small ground island directly beneath the trace, effectively making that layer a mixedlayer?
Any insights would be appreciated. Thank you for your time and help
When I looked at you stackup structure. Please take care the reference plane for layer 6 (which you are going to route the impedance trace on it).
Below are the other details:
You can include other power rails on Layer 5. But critical part is ensuring the VDD_DDR portion remains solid and continuous underneath all components and traces that reference to it.
No need to arrange VDD_CORE closer to a specific layer based on its rank in the power sequence. Focus on keeping your power planes solid and providing good return paths for signals.
For high-speed signals, ground planes should always be solid and uninterrupted path on a solid reference plane.
The order looks good, but the exact distances also matter.
Layer 6 will reference layer 7 as intended, but it will also reference layer 5. That may be a problem if layer 6 signals cross splits in layer 5. Try to make layer 5 be farther away than layer 7, so it won’t be referenced as strongly.
Layer 5 (the power layer) will itself reference a ground plane. Layer 4 may well be physically farther than layer 7, in which case any noise on the power rails will want to pass through signals on 6, and 6 will be noisier than you expect.
To begin with, swap the “impedance-controlled for DDR3 and PHY” from layer 6 to layer 8. This is because the displacement currents that will be generated by these signals will be induced in layers 5 and 7 at present. But layer 5 is segmented and so is discontinuous which messes up the displacement currents and causes EMI. The suggestion made by @JimJJewett is the right way to help reduce the impact - increase the distance between layers 5 and 6, and reduce the distance between layers 6 and 7. But even doing this, putting high-speed signals on layer 6 is still a bad plan. Reserve layer 6 for signals with slow edge rates only.
Now for the questions raised.
(1). You can split the plane on layer 5 just as @dilip has said. The main reason for this advice is driven by the way DIMMs are made where the CA bus references the VDD plane so that the DIMM can be made with fewer layers. When you are using individual DDR3 devices, you can make all signals reference GND, so this rule can be relaxed in extreme cases. However, having a wider, solid plane improves the PDN impedance because the capacitance to the adjacent GND plane is maximised.
There is another thing that you may not have considered, that being where you are going to put the decoupling capacitors for the DDR3 device (and the processing device). If you have them on the top layer (which often works out best) then your planes need to go far enough to reach these parts so that they don’t need long tracks to the vias linking them into the plane. But to get the most out of the power delivery make the core between layers 4 and 5 as thin as possible; this maximises inductive coupling too and thus reduces plane impedance.
(2). As others have said, plane layers and power supply sequencing are independent of each other.
(3). Splitting GND layers is almost never a good thing to do. The saddest thing is that most of the time when application notes recommend splitting the plane (usually because of separating digital and analogue GNDs) what they are giving is bad advice. To find out why search for professor Eric Bogatin and splitting ground planes and you should find this article:
This tells you what the exception could be, and fills in a lot of the detail as to why. So the quick answer is simply don’t split any of your GND planes.