Ask Me Anything with PCB West speaker Syed Ubaid Ali Warsi (high speed and EMC)

Post your questions about high speed and EMC in this thread and Syed will reply on March 20th!

THIS IS NOT A LIVE EVENT. You MUST post your questions ahead of this event so Syed can type in the answers.

For high speed stripline routing, is it acceptable to use GND as one reference plane, and a solid power plane as the other? Do stitching caps need to be used at signal transition vias? Any other considerations?

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Is it possible to route differential Pairs through Vias when the board only has 2 Layers?
Could it work when done like shown in picture 29 and 30?

The reason I ask, is that I use an Stm32F103C8T6 and want to add USB-C. The problem is that the D+ and D- Pins are interchanged.

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Which termination methods do you consider most efficient for managing high-speed signals in HDI PCBs, and how do you determine the suitable termination technique?

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Hi Syed, what is your own personal approach to minimize SI issues, such as crosstalk and impedance mismatches in your high speed designs?

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Hello Syed. Can you recommend some key parameters to consider when selecting high speed connectors? and how do these impact SI and overall performance?

Tho stages of Differential mode filters to meet emc requirement. Is the circuit topology of first stage differential filter with one Inductor correct? or do i add a second bottom inductor to first stage filter? What are the advantage and drawback of two stage differential filter?

Hi Michael,

Ideally the HS trace should be sandwiched between two ground planes but sometime you are constrained and can’t afford two ground planes in that case you can have one layer as power plane but it needs to be same voltage level as the traces you are trying to reference.

Let’s assume we are talking about DDR4 lines along with CLK and DQS pairs, so these trace can only be refenced with 1.2V.

For the high speed transceivers, PCIe Gen2-5 lanes, you must need to have GND planes on both sides.

I deal with pretty high-speed structures like 56gpbs PAM4 and I never used stitching caps.


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Hi Saitter, Unfortunately I don’t see any picture you are trying to show. Can you please resend those?

What I could understand that D+/D- are crossed between host and the device. Yes you can use the two vias to route your diff pair but do add the GND vias on transition vias as it will provide the low impedance path for the signals being transitioned to different layer.

I just realized you are taking about USB-C and if you are going to have USB3.0 running then two layers PCB is not a good idea as you won’t be able to the control the 90 ohms impedance which is essential for 3.0.

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Hi Ravi,

Your layer stack-up is the key, 90% of EMI issues can be resolved if you have well optimized stack-up. You can improve your PDN, Signal and power integrity if your layer structure is good. So this is the first thing I do before starting any layout.

You need to make sure you have the same impedance between driver, transmission line and load. You can use different filed solvers or for a very basic trace width calculation for a certain impedance you could even use PCB TOOLKIT by Saturn PCB, pretty handy and free tool.


Can you be specific what kind of kind of highspeed connectors you are talking about?

Thinking of going with the Samtec diffenrential connectors. Any thoughts on those?

There’s no one-size-fits-all solution for termination techniques. It depends what interface you dealing with.


Thanks for the answer Syed.

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