Ask Me Anything with Karen Burnham


Post your EMC questions below before May 22nd and @karen.burnham will get you the answers!

What advanced techniques do you recommend for effectively mitigating parasitic capacitance and inductance beyond conventional methods, like minimizing trace length or optimizing component placement?

What’s the optimal layer stackup for minimizing external interference in a design to power sensors via low dropout linear voltage regulators? especially considering the need for clean power up to a few hundred MHz for a 10 MHz operating sensor?

What kind of simulation tools do you recommend for predicting and analyzing EMC perf during the design phase?
And how accurate would you say they are?

Could you give an explanation of what exactly is Common Mode Noise? Would you agree that EQUAL Common Mode Noise is NOT injected in Differential Pairs (they are uneven due to distance/geometry), unless the noise source is directly centered and equally spaced between the pairs (either on the same layer or above/below the pair)? [Rick Hartley] What do you recommend for keeping minimal crosstalk levels between single ended or differential pairs? Thank you for your time!

When is it a good idea to split up the ground. For example a metal box connecting to a circuit board ground or connector grounds. In some cases it is recommended to connect the connector shell to the box, but to have a bead separating the connector and box from the PCB ground. More often than not I have found tying the pcb ground to the metal box is the best way to go.

In a multilayer board, can you have inductors in series with the decoupling capacitor?

Would using two unequal decoupling capacitors yield better results for bulk decoupling compared to using two identical ones?

Thanks for your question. Let me start with a caveat that I’m currently employed by a CEM software company, so take my answers with a grain of salt.

The first and oldest tool is a rules-based checker in your layout software. This will check for things like: traces routed too close to the edges of boards, long co-routed traces that have high potential for crosstalk, traces routed over ground plane splits, etc. People complain about too many “false positives” with these tools, but you can tweak the settings to make them more streamlined and useful for you. Not a substitute for a thorough design review, but a good first cut.

Then you’ve got your real PCB modeling tools. I know that EMA (my current company), Ansys, CST, and others have tools that tackle this, such as ANSYS EMC Plus, HFSS, SI Wave, etc. They all have pluses and minuses in terms of their user interface, how much detail they capture and how accurate they are. In all cases, they are valid to the extent that the model matches reality. However, if the model simplifies things (leaving out non-critical nets, having differently shaped enclosures or using different materials, installation conditions), then simulation results will drift farther away from “reality”.

However, consider that the same is true of testing. We test in certain conditions, but as-installed or as-used conditions are almost always different than test setups. That doesn’t mean the tests (or simulations) are inaccurate, it means that they’re a just good guide to ultimate performance, not a perfect match for ultimate performance.


There might be times when you might want to put am inductor in series with a decoupling cap, but they’re probably pretty rare. I think of it this way: with a decoupling cap, I’m trying to give high frequency noise a short path to ground so it can return to its source a “quickly” as possible, minimizing the chances that it will find a way to start radiating. An inductor will act in the exact opposite way, generally blocking high frequency signals. That’s one of the reasons that a simple LC filter has the inductor and capacitor in parallel, not series.


The reason to use different cap values is if you’re concerned about different frequencies coming through. So if you usually use 0.01 uF caps but are worried about them getting overwhelmed by some lower frequency noise (maybe from a nearby SMPS), it could make more sense to add a 4.7 uF cap in parallel instead of several more 0.01 uF caps.

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What is proper way to connect chassis (metal case) to the inner ground?

I would study this one online a bit. I have read bad things about multiple capacitor values because they don’t exactly have that multiple frequency low impedance effect due to the lead inductance. In-fact, according to Lee Ritchey and Henry Ott, multiple capacitor values can create resonant peaks that raise impedance instead of lowering it (depending on your frequency of course)! Check out EMC by Henry Ott, CH 11 and Right The First Time by Lee Ritchey, Volume 1 CH 34.

Common mode noise is one of those topics you can write a textbook chapter about, or maybe it needs its own whole textbook. In general, common mode noise is some kind of signal that is traveling along conductor(s) without any balancing return signal to cancel it out. The return signal is taking some oddly capacitive path back to source. It is never intentional and never shows up on schematics. This can happen for all sorts of reasons, not just when a noise source is equally spaced between two differential pairs. Sometimes common mode noise is caused by a differential pair being unbalanced in some way, so the hot and return currents don’t perfectly cancel each other. But there are plenty of other sources and configurations that can cause common mode noise.

For the second question, avoiding long co-routing is one of the most straightforward ways to avoid crosstalk, as is having ground/guard traces between noisy traces and sensitive ones. Making sure that any high frequency currents have straightforward paths to return to their source, ideally through a solid ground plane, can minimize the mutual inductance between traces that contributes to crosstalk. For wires in harnesses, twisting differential pairs is a great way for them to pick up less noise from the environment.


Generally speaking, you don’t want to split up the grounds unless there’ a good reason. Making the connection with a bead acts as a low-pass filter, allowing DC power to flow through that connection easily but keeping high frequency noise isolated.

In my aerospace experience, we often want to keep DC power isolated from chassis, but want the enclosure to share a ground reference with the PCB to prevent high frequency radiated emissions. In that case, we make a connection between the PCB ground plane and chassis through a known capacitance. (NASA-HDBK-4001 has a variety of different grounding strategies for aerospace/defense projects.)

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Hello! It depends on where you want your low frequency/DC currents to flow and where you want high frequency connections. There’s a good image in this Sierra article showing making a ground connection through a capacitor, which is often a good idea for helping to mitigate radiated emissions from the enclosure.


I’d say that the most important part of the stackup is to have a solid area of ground plane beneath the trace that is running from the LDO to your sensor. That will give any noise on the line a low-impedance path back to source and avoid having it contaminate the sensor signal. Having ground vias to facilitate that noise return path will also help.


Thank you, great article!