How do you approach selecting and placing decoupling capacitors in your designs? Share your strategies for choosing values, placement techniques, and best practices for minimizing noise and ensuring power integrity.
Let’s discuss below PCB people, shall we?
When selecting decoupling capacitors, I always consider their self-resonant frequency to ensure effective noise suppression across the desired frequency range. I also use multiple capacitors of the same value for efficient filtering.
I always place decoupling capacitors as close as possible to the power and ground pins of the ICs to minimize inductance in the power supply path, reducing noise and improving power integrity. For high-speed designs, I also ensure short, wide traces and optimal via placement to further reduce parasitics.
This subject is, sadly, still largely misunderstood, even in SC official learning materials such as
protoexpress.com/blog/decoupling-capacitor-placement-guidelines-pcb-design/
I dare everyone to listen to a minute or two of this lecture:
starting at this particular time that I linked. I promise you that, after watching this, you will want to rewind it and watch it whole. And watch it again! Then, if you still haven’t watched everything you could find on-line by Rick Hartley, you will want to search for all of his lectures. They are just pure gold. You’re welcome!
Marko
Thanks for sharing. I will definitely tell our engineers to watch this. And agreed, Rick’s classes are gold.
In addition to placing capacitors close to the power pins, for high-speed designs, I try to route power and ground planes directly beneath the IC to reduce loop inductance, and when necessary, use embedded capacitance techniques for better power integrity.
I prefer using ceramic capacitors (MLCCs) for decoupling due to their low ESR and ESL, which are beneficial for high-frequency applications. However, for certain low-frequency or high-capacitance needs, tantalum or aluminum electrolytic capacitors might be more suitable.
To minimize noise and ensure power integrity, I always make sure to have a good ground plane in my PCB designs. This provides a low impedance return path for the decoupling currents. Additionally, using multiple vias to connect the capacitor pads to the power and ground planes can further reduce inductance.
One often overlooked factor is capacitor aging, especially for MLCCs. Their capacitance can drop significantly over time due to DC bias and temperature effects. To counteract this, I sometimes oversize the capacitor value or select capacitors with higher voltage ratings to mitigate the loss and ensure long-term stability in critical designs.
Place vias symmetrically and directly beneath the pads when possible, to eliminate trace stubs. This directly minimizes parasitic inductance in the path, significantly improving the capacitor’s filtering effectiveness