Thank you for your interest in our webinar on best decoupling capacitor strategies by Lance Wang of Zuken and @ThePCBGuy.
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You can ask your questions on this thread and our experts will reply.
I’ll post below the questions and answers from the Q&A session we hosted at the end of the webinar.
Q: What is the difference between decoupling and bypass as applied to capacitance?
A: Decoupling capacitors stabilize the power supply, and bypass capacitors filter out high-frequency noise from power or signal lines to the ground.
Q: How does the PDN Analyzer tool help to know what value of decaps is needed?
A: Currently, the tool only helps with the target impedance. We are already working on updating it to include decoupling capacitors in the power rail calculations.
You can try it here: https://www.protoexpress.com/tools/power-distribution-network-analyzer/
Q: How do two local decoupling caps, compared to one cap of double the value, reduce overall inductance and improve filtering efficiency?
A: Using two local decoupling capacitors instead of one with double the value reduces overall inductance and improves filtering efficiency for several reasons:
Lower equivalent series inductance (ESL): By using two capacitors in parallel, their equivalent series inductances are also paralleled. This results in a lower overall ESL compared to a single capacitor.
Lower equivalent series resistance (ESR): Most capacitors have a fixed minimum ESR, typically a few milliohms. Paralleling two capacitors generally reduces the overall ESR.
Consistent capacitance with the exact specifications: If the two capacitors have the same dielectric material, size, and voltage rating, their DC bias effect will be similar to that of a single capacitor with double the value.
Consideration of different specifications: If the capacitors differ in size, voltage, or dielectric material, their combined capacitance might not precisely match that of a single capacitor with double the value. This needs to be considered when selecting capacitors.
Q: What package size is best for the decoupling capacitor closest to the IC for power integrity?
A: The best package size for the decoupling capacitors closest to the IC is the smallest one available for power integrity.
This is because:
Smaller package sizes have lower ESL. Minimizing ESL is crucial as we get closer to the ASIC, which is why smaller capacitors are preferred.
A wide geometry is better than standard aspect ratio capacitors because they have lower inductance.
Capacitors usually connect to the IC through PCB vias. These capacitors are often on the backside of the board, while the IC is on the top. The via inductance can become significant than the capacitor’s ESL. Therefore, careful attention must be paid to the geometry and physical location of the vias relative to the capacitor pads to minimize overall inductance.
It’s essential to aim for the ESR of the decoupling capacitors to be close to the characteristic impedance of the IC package. This includes the onboard package capacitors and the inductance leading to the die. If the ESR is too low, it can increase the internal package resonance’s quality factor (Q), potentially worsening signal integrity.
Q: What are low ESR and low ESL values? How can we identify whether they are low ESR or ESL?
A: Low ESR (Equivalent Series Resistance) and low ESL (Equivalent Series Inductance) indicate minimal internal resistance and inductance in capacitors and inductors. The datasheet for each component specifies this.
Q: What was the problem with the red components in the BOM?
A: The issues could be related to duplicates, wrong MPNs, mismatch in the reference designator and quantities, etc.
Q: The data sources for BOM validation are from Digikey and Mouser. If a part is not available at these two sites, then what? In Altium similar is already available.
A: We are checking customer inventory, then Sierra inventory, and then distributors. This is a little different from Altium’s feature.
Q: How the size of the decaps affects the ESL?
A: Smaller package sizes generally result in lower ESL. This is why choosing the smallest possible package size for decoupling capacitors is essential for minimizing inductance.
Q: On p.12 of the first pres., why place the cap close to the via? I think the total length (total loop inductance) will be significant.
A: Placing decoupling capacitors close to the vias reduces the inductive path length. This minimizes the parasitic inductance, which helps maintain the capacitors’ effectiveness at high frequencies. Proximity to vias ensures that the capacitors can quickly supply or absorb charge, stabilizing the voltage levels at the ICs.
Q: I have some basic questions: in the demo of the PDN analyzer, what was the switching current on the PDN analyzer? What is the difference between bypass capacitors and decoupling capacitors?
A: The percentage of switching current is determined based on the total swing magnitude relative to the maximum current (Imax). A decoupling capacitor stores energy in a localized manner. A bypass capacitor prevents noise from entering the system by bypassing it to the ground.
Try the tool here: https://www.protoexpress.com/tools/power-distribution-network-analyzer/
Q: I think that using 3 different value capacitors creates resonance; instead it is better to use 3 equal value caps.
A: Using three different value capacitors can indeed create resonances at various frequencies in the power distribution network (PDN). Instead, it is generally better to use three capacitors of equal value.
Here’s why:
When different capacitor values are used, they can resonate at different frequencies, potentially causing peaks in the impedance curve that exceed the target impedance. This can lead to noise and instability.
According to Istvan Novak, a well-known figure in power integrity, multi-pole decoupling involves using various capacitor values to create a broad noise suppression pattern. The goal is to maintain a peak below the target impedance across a wide frequency range. This approach requires careful planning and execution to avoid unwanted resonances.
To achieve optimal decoupling, you can calculate the exact capacitance needed for any location on the board using the formula: C = L / (R²), where L is the inductance of the power plane at that location, and R is the target impedance.
The Equivalent Series Resistance (ESR) of the capacitor should be close to the target impedance. Achieving this helps maintain a flat impedance profile. However, it’s challenging to balance low inductance with appropriate ESR. Paralleling capacitors can reduce inductance but may inadvertently lower ESR too much, causing new resonances.
Historically, capacitors with controlled ESR, like the Sr. ceramic capacitors from TDK, were designed to address this issue. However, these capacitors became less popular and more expensive due to misconceptions about the importance of specific ESR values.
Q: For higher frequencies bypassing, which dielectric is better, COG, x5R, X7R?
A: When considering dielectrics for higher frequency bypassing, the options are C0G, X5R, and X7R. Each has distinct characteristics:
X5R dielectric:
High capacitance density: X5R capacitors offer the highest capacitance in the smallest size, making them ideal when you need a large capacitance with low ESL.
Temperature stability: X5R is less stable with temperature changes.
DC bias effects: X5R has significant DC bias effects, which can reduce the actual capacitance to as low as 30-50% of the labeled value under certain conditions. This variability must be carefully considered in your design.
X7R dielectric:
Better stability: X7R capacitors are more stable than X5R with respect to temperature and bias effects.
Moderate capacitance: While not as high in capacitance density as X5R, X7R still offers a good balance between stability and capacitance.
C0G dielectric:
High stability: C0G capacitors are highly stable with temperature and voltage, making them excellent for RF frequencies.
Low capacitance density: C0G capacitors provide lower capacitance than X5R and X7R, which can be a limitation if high capacitance is required.
To determine the best dielectric for your specific application, consider the required capacitance and the equation:
C=𝑳/𝑹^𝟐
This equation helps you calculate the necessary capacitance based on the inductance (L) and the target impedance (R). Select the dielectric that best meets these requirements while considering stability and bias effects.
Q: Is x2y preferable for bypass/decoupling applications than others?
A: X2Y capacitors are preferable for bypass/decoupling applications due to their lower ESL than standard 2-terminal capacitors.
Here are the 4 key points to consider:
Lower ESL: X2Y capacitors are 3-terminal devices designed to provide lower ESL by having a shorter electrical length from each end of the device to the middle pad. This makes them more effective in reducing high-frequency noise.
Via inductance: If you place X2Y capacitors on the bottom side of the board for an ASIC, you still have to account for the inductance of the vias connecting them to the top side. The via inductance can sometimes offset the benefits of the lower ESL of X2Y capacitors.
Space considerations: While X2Y capacitors are beneficial in reducing ESL, they require more board space than other capacitor configurations. An alternative is to use smaller capacitors placed end-to-end, which can mimic the performance of X2Y capacitors. Using wide geometry capacitors in this configuration can further reduce ESL.
Q: What is the cap value in the bypass filter for reducing bump at 260 kHz?
A: To reduce the bump at 260 kHz in a bypass filter, it’s important to understand that the bump is caused by the resonance of an inductance and a capacitance with a quality factor (Q) greater than one. Here’s how you can address this:
Understanding the bump: The rising side of the bump (to the left of 260 kHz) is due to the inductance, while the falling edge (to the right of 260 kHz) is due to the capacitance.
Correct capacitance value: To reduce the bump, you need to ensure that the capacitance is sufficient to absorb the inductance. The required capacitance can be calculated using the formula, C=𝑳/𝑹^𝟐, where L is the inductance and R is the target impedance.
ESR matching: Additionally, the ESR of the capacitor must match the target impedance. This helps in flattening the impedance curve and avoiding the bump.