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Adding decoupling capacitors of varying capacitance values creates resonant peaks. Is it not better to use several capacitors of the same value in parallel if higher capacitance is required?
Does the 3W clearance apply to signal-ground connections, or is it specifically meant for signal-signal connections?
Hi Dan, is it a best practice to arrange vias uniformly to avoid EMI? In the past, I received a suggestion to scatter the vias in a more random fashion.
Hi Dan! Is it necessary to place the capacitor with the lowest value closest to the power supply? If so, why?
Hello Dan. How important is trace gap for crosstalk mitigation? Is smaller better?
Dan, if I connect a via from a ball to a capacitor on the bottom side of the board, that via also touches the power plane. Is the discrete capacitor a better energy storage device than the capacitor created between the power plane and the ground plane?
Can you explain the consequences of using a pwr plane as conductor in a dielectric waveguide?
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Hi Dan, What new technologies and workflows do you see maturing/becoming more relevant for optimizing EMC performance in the coming decade (automotive sector)⌠excluding numerical (EM) simulation.
What are your thoughts on automated design rule checkers (geometry based âsimulationâ) to check for EMI violations (e.g. traces running over split ground plane, switching references without via pair, etc) at the layout stage (ODB++ files).
Hello Dan,
When using a current measurement circuit (measures the voltage drop across a sense resistor) that has it own isolated power supply and reference plane, how should the differential signals be routed from the sense resistor to the differential input of the measurement circuit? The measurement circuit is on a daughter card solder to the main board like a card edge PCB, Vertical?
What are some common EMI issues you see when designing a switched mode power supply?
This is an important question. Dr. Todd Hubing says that the key is the capacitor package, and he specifically says not to mix values. For each package size, the values should be the same. I use a scheme where I place the smallest package capacitor I am allowed to use as close to the IC power pin as possible (I use one for each power pin if possible). I also try to use the largest value that I can. This first capacitor will by virtue of its close proximity and small package be able to provide the fastest response to energy demands driven by the IC transistors it is feeding. The closer these are, the shorter the cycle time for the energy request (depletion wave) to get to the capacitor and to return to the IC (sourcing wave). The larger energy storage capacitors can be place farther away. For the larger local capacitors, and for the output storage banks near the power supply, multiple capacitors of the same value will provide a stable source of energy. The beauty is that these capacitors provide parallel impedances, so the result will be more energy delivered to the load for each wave cycle. For example, four 10 uF capacitors are better that one 47 uF capacitor because they can deliver more energy per wave cycle. Of course, cost is often a major concern, but if you can get the smaller values in a smaller package, it may be that the cost is similar.
So, the short answer is, âyes.â
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This is important for signal-to-signal separation. The actual spacing depends on the switching speed of the signal, not the frequency (pulse recurrence time). Crosstalk occurs at the wavefront. The changing electric field in the space between the signal trace and the ground plane creates a changing magnetic field in the signal trace. The changing magnetic field in the signal trace creates a changing electric field in the adjacent space. This second changing electric field will create a changing magnetic field in the next trace. This second changing magnetic field will cause a changing electric field in the next signal space. This will cause distortion in the signal that is traveling in that dielectric. The magnitude of the resulting distortion is a function of the distance between the two signal traces. This interaction is reduced by the square of the distance. The faster the signal switches, the higher the interaction between the signal conductors. The final answer is something Rick Hartley often says, âIt depends.â For most signals, 2W is sufficient. For faster busses, such as DDR4, Serdes and PCIE Gen 4, 3W is probably required. Unfortunately, 3w is difficult to achieve because of the small pin pitch in most new ICs. You can only try to get the signals out into the open where you can increase the separation and keep the closer spaced traces as short as possible.
For the signal to ground perspective, such as ground flood, the issue is the same, but because the ground flood copper will invariably be much larger than a signal trace, and the magnetic field induced into this conductor by the changing electric field in the space separating the signal trace and the ground flood will be much lower in magnitude because it will be spread out across a larger area, and be less likely to cause disturbance in signals on the other side of the ground flood.
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It is important to place the smallest package capacitor close to load. This value should be as large as practical. At the power supply, you donât need small value capacitors or packages. The switching speed of the power transistors is extremely slow compared to the switching speed of the transistors in the load. Placing large package capacitors with the required amount of total charge storage, reasonably close to the regulator, is important, but small packages with small values serve on purpose here.
I am not sure what vias you are talking about. Ground transition vias are key to good signal integrity and EMI control. I always place them as close to the signal vias as allowed. For large areas of ground copper, placing vias across the structure, whether they are uniformly placed or randomly, does nothing at all. For field to be contained, you need two distinct conductors separated by a space. In this case, they are all the same conductor, and therefore this space fails the test to see if it can store field.
For good power delivery in the Z axis, interleaved power and ground vias are required, not big blobs of each kind or large vias. Interleaved vias form multiple parallel Z-axis transmission lines connecting the horizontal dielectric layers in what I call a âwaterfall.â
For my ground flood areas, I add a ground via wherever they cross on other layers, to help form a pseudo-Faraday cage in my PCB structure. For the boundary edges of ground flood structures, sometimes I do have perimeter stitching vias, but only if the signals that are adjacent to these flood areas are switching faster than 200 pS.
Sometimes designers want to do this around the perimeter of the board, to reduce âedge radiation.â However, edge radiation occurs if the distance from the signal via to the edge of the PCB is less than the distance to the nearest ground stitching via. Another reason to make sure you use them.
I refer you to the earlier answer for PoulomiG.
This is important for signal-to-signal separation. The actual spacing depends on the switching speed of the signal, not the frequency (pulse recurrence time). Crosstalk occurs at the wavefront. The changing electric field in the space between the signal trace and the ground plane creates a changing magnetic field in the signal trace. The changing magnetic field in the signal trace creates a changing electric field in the adjacent space. This second changing electric field will create a changing magnetic field in the next trace. This second changing magnetic field will cause a changing electric field in the next signal space. This will cause distortion in the signal that is traveling in that dielectric. The magnitude of the resulting distortion is a function of the distance between the two signal traces. This interaction is reduced by the square of the distance. The faster the signal switches, the higher the interaction between the signal conductors. The final answer is something Rick Hartley often says, âIt depends.â For most signals, 2W is sufficient. For faster busses, such as DDR4, Serdes and PCIE Gen 4, 3W is probably required. Unfortunately, 3w is difficult to achieve because of the small pin pitch in most new ICs. You can only try to get the signals out into the open where you can increase the separation and keep the closer spaced traces as short as possible.
For the signal to ground perspective, such as ground flood, the issue is the same, but because the ground flood copper will invariably be much larger than a signal trace, and the magnetic field induced into this conductor by the changing electric field in the space separating the signal trace and the ground flood will be much lower in magnitude because it will be spread out across a larger area, and be less likely to cause disturbance in signals on the other side of the ground flood.
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There is very little energy stored in the PCB dielectric. Capacitors are far better structures for storing charge. Ceramic capacitors have a Dk in the order of 30,000, compared with roughly 4 for PCBs.
I donât use power planes, only power islands. For BGAs, where possible, I place the capacitors directly between the ball sites. I ensure that there is nothing routed between the power and ground vias so there is an unobstructed path to and from the capacitors. Especially in the case of multiple power balls, I can provide parallel connections between the IC, the power island / ground plane space, and the capacitors.
The power delivery goes like this. Distance / travel time dominate. The capacitors under the BGA supply power to the BGA (closest.) The power islands / ground plane structure delivers energy from the local large capacitors to the small capacitors. The SMPS output structure delivers energy to the local large capacitors. This interaction is driven by the impedance of the connecting transmission lines and physical distance between the sections.
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In nearly every case in an electronic design, the signals come from switches that are supplied energy from a power supply that is connected using a âpowerâ conductor and a âgroundâ conductor. The output from the switch still has to go into a transmission line that is bounded on one side by the ground conductor (hopefully a ground plane.) This structure must be kept intact from the power supply through the switches to the final load. The energy travels in the space between the signal conductor and the ground conductor.
To use power as a âreturnâ, you have to charge the space between the power and ground conductors, which will take more energy and more time. This causes a temporal distortion in your signal. The larger the space (higher the impedance) the worse this is. Since this is an unbounded event, and the chances of this being the only signal that is referenced to power are very low, other signals are forced into this same scenario, and now you add crosstalk to the temporal distortion. Two bad things that affect signal integrity and EMC. Then, because the receiver expects signals referenced to ground, this has to happen in reverse. Using power as a return will result in the signals being distorted in at least four ways. Why would I ever mess up my signals on purpose? Also, since planar capacitance is really insignificant, I would never use power planes anyway. I use power islands adjacent to ground planes and use these as low impedance connections between my IC power pins, the small close capacitors, and the larger local charge wells.
Bottom line is, donât use power as a return.
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I think the key is tools that link the three-dimensional PCB structures to their electrical simulation software. Dielectric awareness is critical, and that requires identifying and understanding the existence (or omission) of good transmission line principles. Most tools are not dielectric aware and are not capable of evaluating the entire structure. This perspective is critical to any type of automated evaluation, or more importantly, design tool.
What good is an auto router if it doesnât route good transmission lines? (Where is the ground plane? Ground transition vias, yeah, right, what are those?) What good is a PDN simulator if it canât tell the difference between a poor board stack up or a good one?
Maybe this isnât as much of an answer as it is a call for action from the tool vendors.
If you can develop a solid board stack up, and route good transmission lines (staying one dielectric from ground), then and only then will the tools tell you how good the design is. But you canât depend on it to tell you if you did not follow the one dielectric rule.
I only wish this wasnât the case. Too many teams reap the results of this issue, and even with sophisticated analysis tools still have to go through multiple spins of their design. Like I said in my article, this is a billion-dollar mistake.
The hardest seem to be lower frequency conducted emissions. I am actively engaged in research where I have designed multiple versions of the input circuit for an SMPS, with changes in components and PCB dielectrics. Feeding the depletion waves is the goal, and I have found that having ceramic capacitors placed close to the input to the SMPS can be just as effective as a PI filter with a huge inductor and capacitors. There needs to be more research in this area.
I believe radiated emissions are not as difficult to manage. Inductor orientation is one of the issues I have seen. The input to the windings should always touch silicon. This is so the most aggressive EM wave will go inside the structure and reduce the impact of the switching events.
Routing between components that are placed on opposite sides of the board also are a source of problems. The energy will be moving in the outer dielectrics, and these must be connected in the Z-axis to work properly. I often see either a blob of power vias, or a large via, connecting the SMPS IC to parts on the bottom of the board. These donât provide a good Z-axis connection between the horizontal dielectrics. I recommend interleaved power and ground vias to make these connections. Just take a look at the newer BGA parts, and you will often see a checkerboard in the center of power and ground balls for the core supplies. Waterfalls!
Another issue is the use of heavy copper for power delivery. The energy is traveling in the dielectric, so changing from one-ounce copper to two-ounce copper doesnât; change the dielectric, so does not increase the current carrying capability The dielectric stays the same. It just means that the board can take more abuse before it catches on fire. More copper for heat dissipation is good, but for more power you need lower impedance.