I have found the attached screenshot from Siemens presentation. The VCC1 and VCC2 are two different power supplies with different voltage levels. How do we connect a de-coupling capacitor between two power planes.
Let’s say on L2 we have 3.3 V and 1.8 V planes. Can we mount a SMD de-coupling capacitor on L1 and attach one terminal to 1.8 V and the other terminal to 3.3 V through vias ?
What you say is correct. One terminal of the capacitor connects into the VCC1 plane and the other into the VCC2 plane. But this is not a panacea.
If the edge rates on the signal that crosses the plane split are moderately fast (faster than 20ns rise or fall time) then the inductance of the capacitor will mean that the displacement current in the planes will not entirely propagate through into the other plane. To make matters worse, the inductance of the vias and PCB traces connecting the capacitor result in the performance being worse than anticipated. Also, the further the capacitor is from the point where the signal crosses the gap, the worse the performance will be. While it is true that many circuits will still continue to work (even when you forget to fit the capacitor to the PCB) the problem is that the EMC levels radiated by your board will rise.
solutions: (1) don’t cross split planes. (2) put a 0V plane between the signal and the split plane. Both of these give perfect solutions to this problem. When you cannot do either, the bridging capacitor is your only method, and it does help, but don’t expect too much from it as it is only a fair compromise at best.
I understand.
Solution 1: Do not route high speed signals over a split in the reference plane.
Solution 2: Place a ground plane between the signal and the split plane. Consider the signal is at L1 and the split plane is at L2 then where we put ground plane ? On L1 ?
Can we route a wide ground trace all the way along the routed signal on L1 ?
Coming back to bridging capacitor. The bridging capacitor can be between two voltages, for example VCC1 = 1.8 V and VCC2 = 3.3 V. Is that possible ?
Answering the question about where to put the GND plane, the answer is that the signal is on L1, the GND plane is L2, and the split plane that was on L2 is now on L3. Don’t forget that the stack-up needs to be symmetric or it will warp when you assemble it. This means that you are now at a 4-layer thickness if there are no signals on L4 that need to cross the plane cut on L3. But if there are signals there, this means you are at a 6-layer board (sig - GND - split power - split power - GND - sig). The real question is whether you can reduce it down to 4-layers by not using power planes with splits in and just routing them as wide signal traces? It is almost certain that changing to 4-layers and using Sig/routed power - GND - GND - Sig/routed power where the GND planes have no splits in them fixes the problem.
The idea of having wide GND traces on L1 is a good question to ask, but it does not work. Being realistic, the signal on L1 may be 100-200um wide, and is perhaps 100um above L2. The adjacent GND trace cannot be closer than 100um away from the signal trace, and is only 18um thick (normally). The coupling between the signal and the split planes on L2 is probably 10x stronger than the adjacent GND trace, so in practice the GND trace makes no real difference. Also, the GND trace will pass over the split and any coupled signal present in the GND trace will also be radiated in part from the L2 split - so you really gain nothing.
Last question, can a capacitor be placed between a 1.8V supply and a 3.3V supply? Answer, yes, of course. The capacitors will see a voltage of 3.3 - 1.8 = 1.5V permanently present, but this is not an issue. It is just a less than ideal solution and you will see the result of it in the EMC test chamber. You may be lucky and it works well enough to pass the test, but there again, you may not. Crossing split planes (even if both sides are the same voltage as in a GND plane split) always causes problems.
Usually two capacitors are located close to the signal that crosses the break plane, but this is not a good solution. Capacitors don´t do a good job at high frequencies because capacitors become inductors. Regarding the small GND plane, keep in mind that return plane has to be at least 3 times the track width (5 better).
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