Stitching via

I have found some text regarding stitching via. I am wondering how about if the two reference planes are power planes with different voltages on them. Can we also put stitching via using capacitor between them if a high speed signal is routed over the split ? How about if we have 1.8 V and 3.3 V as reference power planes for high speed signal ?

Can this be two ground planes ? for example analog ground plane and digital ground plane ?

In case they are power and ground plane then it’s fine to use decoupling capacitors. But how about if both of them are power planes or both of them are ground planes ? Can we use capacitors to stitch them ?

Generally, stitching vias are used to connect two ground planes together.

If you have two ground planes, you can use a capacitor alongside a stitching via to make sure the return path is routed cleanly.

I’m not sure what to say regarding your ref power planes. I don’t understand why you would want to do that. Can you explain?

You can read more here Here is why you should use Via Stitching for your next PCB Design

Thank you very much for your comment. I understand you mean that if there is a split in the ground reference plane having same potential for example DGND which we normally used to represent digital ground for digital signals. If we are routing a digital signal and there is a split in the reference plane means split in the DGND than we can use “stitching via” to cover the distortion caused by the split and then the reference plane would be more towards continuous.

In some designs I have seen power plane as reference for signal layers. If there are two power planes and they are separated by for example 40 mil which is a split. Can we also use the stitching via in that case as well ?

I’ve shown your question to our design team and they don’t understand this scenario. They say this doesn’t make sense to them. Can you DM me if you want to explain over a quick call?

Consider two case:

[L1: Signal L2: Ground]: If we route a signal on L1 and these exist a split in Ground plane in L2. Can we mount a capacitor on L1 with both terminals connected to Ground plane through via ?

[L1: Signal L2: Power]: If we route a signal on L1 and these exist two power planes in L2 at different voltage levels. Can we mount a capacitor on L1 with both terminals connected to voltage levels each power plane through via ?

Our design team still doesn’t think that makes sense. You should get on a call with us.

Thanks for the message. I think the section stitching via in the e-books need some explanation especially when it comes to the reference planes split then the books suggest to use the “capacitors” mounted on the top layer and use stitching via on each side of the capacitor to the reference plane. The signal is routed on the top layer and the reference planes are located on the 2nd conducting layer, see the picture in the first post which I have taken from the e-book.

This needs some more details. Can reference planes be at two different voltages for example two power planes ? and we can still use the stitching via ? If the reference planes with a split in between are at same voltages can we still use the stitching via ?

It may be possible but it certainly doesn’t sound like a good idea. You can’t have two ref planes to begin with. Can you send a picture of your design?

I have tried to attached “General High Speed Signal Routing” a TI document SPRAAR7J – NOVEMBER 2018 – REVISED FEBRUARY 2023

Here is the link

Section 2.4 describe that there should be no void and no slit in the reference planes. The pictures are shown in Figure 2-6 and Figure 2-7 respectively.

And then there is a text on the
“If routing over a plane-split is completely unavoidable, place stitching capacitors across the split to provide a
return path for the high-frequency current. These stitching capacitors minimize the current loop area and any
impedance discontinuity created by crossing the split. These capacitors should be 1 μF or lower and placed as
close as possible to the plane crossing. For examples of incorrect plane-split routing and correct stitch capacitor
placement, see Figure 2-8 and Figure 2-9.”

Figure 2-8. Incorrect Plane-Split Signal Routing
Figure 2-9. Stitching Capacitor Placement

My questions is on stitching capacitor placement shown in Figure 2-9.

Is it necessary to have both planes same potential and same net names ? and we can only use the stitching capacitor if the planes which have a split have same net name ? for example they have to be AGND and AGND or DGND and DGND. Then we can use stitching capacitor between AGND and AGND or DGND and DGND ? Assuming that the split planes are either AGND or DGND ?

How about if the reference planes are not same and they have two different plane net names for example AGND on one side of the split and DGND on the other side of the split. Can we still use stitching capacitors if the planes belong to two different net names ?

Send us screenshots of the figures.

Figure 2-8 and Figure 2-9 are attached.

Yes, you should do that.

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Yes, as long as the net names are the same.

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Again, I don’t know why you would want to do that. It doesn’t make sense.

I think I see where the communication was breaking down.

An ideal reference plane is infinite. You never come anywhere near the edges, so you don’t need to worry about boundary conditions.

In the real world, infinity doesn’t exist, and you make compromises. The Sierra team is used to talking about which compromises are acceptable.

A reference “plane” is just a polygon fill/copper pour, though it might extend to the entire size of the board on some layers, and it will probably have a few holes in it, for vias if nothing else. As long as your return current stays “far” from the edges/holes, this will be good enough.

On the other hand, you also want each component (or at least each type of noisy or noise-sensitive component) to have its own ground plane, and if they’re going to talk to each other, your signals will have to cross that gap between planes somehow.

Figure 2.6 shows a track just leaping over the gap. The DC return current will eventually find a way, but the high speed AC stuff (including what happens when a signal switches on or off) will hit a wall and angrily radiate in all directions, so that you have crosstalk/interference and fail emissions testing. Figure 2.7 moves the “plane” boundary a little so that isn’t a problem.

But if you must cross the gap, because you’re talking to some component on the other side?

Usually, the least bad option is to just combine the ground planes beneath the two components, so the trace never leaves its plane.

Usually, the next least bad option is to join the two “planes” at a single “point”, and to route the signals over that join point. (You can look up star grounding, but be aware that much of what you’ll find was written assuming audio or 1980s tech, so the unwritten assumptions will be different from the unwritten assumptions for anything labeled High Speed or digital, let alone RF or microwave.)

If you can’t do star grounding either, then you can link the planes with something less than a direct electrical connection; capacitors are a common choice.

Going from the top layer to the bottom layer, and therefore switching to an entirely different layer for the reference plane, is fairly common. If that new reference plane is a power plane instead of a ground plane, then you don’t want to actually connect them and create a short-circuit. Linking them with a capacitor is sometimes a good enough compromise, but it is still a compromise, so the experts are hesitant to recommend it.

The same applies if your ground “planes” are both power planes, but at different voltage levels, or even if they’re both ground planes that you’re just isolating from each other, like your analog ground vs digital ground example. A capacitor may be the least bad compromise, but it is worth first taking another look at avoiding the plane split entirely.

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