Routing a signal trace over a split reference plane

I have some questions regarding routing a signal trace (L1: top layer) over a split reference plane (L2: second layer).

I found a document “General High Speed Signal Routing” a TI document SPRAAR7J – NOVEMBER 2018 – REVISED FEBRUARY 2023. I tried to upload but it does not work. Anyways, here is the link to the document. Otherwise this can be downloaded from the internet easily.

Here is the link.

Section 2.4 of the document describes High Speed Signal Reference Planes. ideally there should be no void and no slit in the reference planes. The pictures are shown in Figure 2-6 and Figure 2-7 respectively. These pictures are attached.

The document also says “If routing over a plane-split is completely unavoidable, place stitching capacitors across the split to provide a return path for the high-frequency current. These stitching capacitors minimize the current loop area and any impedance discontinuity created by crossing the split. These capacitors should be 1 μF or lower and placed as close as possible to the plane crossing. For examples of incorrect plane-split routing and correct stitch capacitor placement, see Figure 2-8 and Figure 2-9.”

Figure 2-8. Incorrect Plane-Split Signal Routing
Figure 2-9. Stitching Capacitor Placement

The pictures are attached.

My questions is on “stitching capacitor placement” shown in Figure 2-9.

Consider two case:

[L1: Signal L2: Ground (GND)]: A signal trace routed on L1, the top layer and these exist a split in Ground plane “GND” in L2. How do we mount stitching capacitor ? Given there exist a split in the ground reference plane (GND) on L2. Probably we mount a stitching capacitor on L1, the top layer with both terminals connected to ground reference plane (GND) through via ? Is that correct ?

[L1: Signal L2: AGND and DGND]: Instead of a split, there are physically two reference planes on layer L2. The signal trace on L1, the top layer has to be outed over AGND and AGND located on L2. How do we mount stitching capacitor in this case ? A part of the signal on L1 is routed over AGND and the other part of the signal on L1 is routed over DGND. Both AGND and DGND are located on L2. Do we need to mount stitching capacitor ?

Can @JimJJewett and @jonathan.lloyd.riley help you out with this one?

Taking the two cases that you mention in order …

First case: GND on Layer 2 with a split, such that both sides of the split are GND. The capacitors should be placed just like the example given in the Texas Instruments document that you referenced. See fig. 2.9, thus linking the GND on either side of the split together.

Second case: As above except that one side is AGND (presumed quiet) and the other side is DGND (presumed noisy). The capacitor placement is exactly the same as the first case. See fig. 2.9 in the TI document.

Well, those are the answers to the questions asked, but no consideration has yet been given to any limitations. So let’s have a quick think about that.

Obviously this is an AC issue, for DC the return current path takes the route of the lowest “Resistance”, and the presence of the split is unimportant. For AC, this is not the case, the impedance is what matters (until the frequencies get very high, then other rules start to apply).

The document suggests something like 100nF or 1uF capacitors, but what do these look like in the frequency domain? A typical 0402 capacitor of 100nF looks like a capacitor, but only up to around 50 MHz, above which the inductance of the part dominates. To make matters worse, the GND plane is on an inner layer, necessitating vias, which increase the inductance and therefore lowers the point where the capacitor becomes inductive.

Now let’s add some reality to this and assume that the signals crossing the split in the plane are fairly modest USB2 signals. Bit rate is 480Mbps, so fundamental frequency is 240MHz which is already 5x the inflexion point on the capacitor’s impedance curve. This is not a good start. Plus the harmonics, which will all be at higher frequencies still. In short, some of the displacement current will pass through the capacitors, but there will be significant amounts of energy directed along the direction of the plane split - and this will radiate giving you EMC problems.

What can you do? Increasing the capacitance does not work because the point at which it becomes inductive is almost entirely a function of physical size. A 0805 capacitor is worse than a 0603 capacitor which is worse than a 0402 etc. In real life there is not much you can do. And the fact that a differential pair crossing a split plane is not as bad as a single-ended signal crossing a split plane is ture but in practice the difference is tiny.

So when can you use this technique of using capacitors to bridge the gap? From about 1 kHz up to about 50-100 MHz (highest frequency component), and be aware that it is a compromise, and not a very good one at that. Above 100-200MHz, this is not a good plan and you can expect trouble in the EMC lab.

Alternatives: don’t cross a split, go round it. Keep your signals over an unbroken bit of the plane.

What about the situation where you have two different voltages, say you make one be GND but the other is 1.8V, then the capacitor solution is about all you can do. Definitely not ideal, but you might be able to make it work if you’re lucky.

Then there’s the case of AGND and DGND. If you put capacitors between the two, this is going to couple noise on DGND through to AGND. True. The obvious next question if at some point AGND and DGND are joined together is whether they should have been split in the first place! In most (but admittedly not all) cases, the plane split does more harm than good and is better removed and just have a solid unbroken GND.

Any other possibilities? Yes, both optical and magnetic coupling devices are available from a number of sources now. They aren’t cheap, but they do work nicely. They are usually limited in the highest frequency you can transfer, but they may be worth considering.

Bottom line with split planes is don’t split them. If you absolutely must split the plane, don’t let signals cross the split. Anything else makes for hard work. It can be treated as described above, but be aware of the limitations.


@Sajal_ee I’m assuming you could no longer find the thread at Stitching via - #16 by JimJJewett
There are more answers there (and above, in that same thread).

But just in case the problem is instead that the answers don’t make sense, I’ll try a different analogy:

If you’re bleeding, a bandage will not fix everything, but it will probably help.

A Stitching Capacitor is a bandage. It will probably help, but even if things go perfectly, it would have been better to not need one.

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Thanks for your comments.

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The stitching capacitors act the same and should be placed the same. Again, better not to split the plane. Maybe look around for some places you can add a zero ohm jumper to avoid it.


I full agree with the Jonathan answer and I don´t have so much to add. What I have seen is that instead of using one capacitor use two, one on each side. I give you other alternative. I suppose the signal you want to cross is somehow “high data rate”. If it is like this, consider change the single ended signal to differential and try to increase the distance between Top Layer and Second Layer. If you do that the return of data+ will be data - and the return of data- will be data +. If the differential lines are quite close one each other there will no interaction between the line and the reference ground (AGND or DGND) and the signal can cross the gap without a big distortion. Once you cross the gap you can back to single ended. Good luck.