Reference plane requirements for controlled impedance routing

Design and Layout
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I know this might be a basic question, but I still want to ask to be sure I understand it correctly. I’ve been learning about controlled impedance routing in high-speed PCB design, and most resources mention that controlled impedance traces should have a reference plane directly underneath them, typically a solid ground or power plane.

I understand that the reference plane provides the return path for signal current. My question is: Why does the reference plane need to be directly below the controlled impedance trace? What happens if, instead, the layer below is another signal layer and not a continuous plane?

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You are on the right track! Just think about it in a slightly broader sense. You ideally want a solid reference underneath and/or around every fast signal trace. Not just the controlled impedance traces. Otherwise the return current will not be well defined (not by you, it will be defined by laws of Physics but you will most certainly not like the implications of having it out of your control). Hopefully this strarts you thinking about what signals actually are and how they propagate through your interconnects. I recommend watching every single lecture you can find on-line by Rick Hartley, not to mention all other giants in the industry. I don’t want to overwelm you at the very start but there is no lack of resources on this topic. You are about to learn a lot, enjoy every bit of it!

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Just think about one very important topic. The energy is located between the track and the return path. This is the place where the electrical/magnetic fields are located. If any other signal is in between will be “contaminated”. It doesn´t matter if the signal is high or low data rate, return path has to be as close as possible to the track and just dielectric in between.

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If you place a signal layer between a controlled impedance trace and its intended reference plane, you’ll disrupt the electromagnetic field distribution and create unwanted interactions.

Specifically:

  • Impedance deviation: The signal layer introduces a parasitic conductive structure that alters the effective dielectric environment. Even a short section of this can locally lower the impedance of the trace above it.
  • Unintended coupling: Nearby signal traces on the intermediate layer can capacitively or inductively couple with your controlled impedance trace, leading to crosstalk or noise pickup.

If it’s just one crossing trace at a right angle, the impact might be minor. But a full signal layer introduces enough interference that you can no longer treat the trace as truly impedance-controlled.

In practice, it’s better to adjust your stackup so that signal layers always reference a continuous plane. If that’s not possible, the trace shouldn’t be considered impedance-controlled. Controlled impedance depends on a well-defined reference environment. Breaking that assumption, even locally, undermines the benefit.

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In a DC circuit, or one operating at up to perhaps just 1 kHz (and certainly by 10 kHz) these low frequencies flow in the path of lowest resistance. These can be anywhere on (or off) your board. Whatever the path, if it is the lowest resistance, that is where the currents flow. But this all changes at higher frequencies.

Once above 10 kHz the signal in a trace induces a flow of current in the opposite direction in any metal close by because of mutual inductance. The closer the metal, the greater the coupling, the lower the impedance thus the energy concentrates between the trace and the nearest metal. This nearest metal is usually the next layer above and/or below the layer on which the trace of interest is found.

Let’s consider how this might look on a real board. Suppose the trace is 100um wide (we can ignore the length, and we’ll think about the trace thickness later), and in your stack-up it is separated from the next adjacent metal layer (which should be a plane) by a prepreg of 50um thickness. We can create a Figure Of Merit to indicate the preferential path which reflects the fact that a wider trace increases the coupling and a smaller gap also increases the coupling. So FOM = W / G where W is the trace width and G is the trace to plane gap. (Note: do not push this comparison too far, it is an indication only, makes certain assumptions, and at very high frequencies other effects confuse matters). So what is the FOM with the numbers we’ve just given: FOM = 100/50 = 2.

Now lets suppose there is copper next to the trace (say there is another nearby trace, or it could be a 0V plane or something else), suppose it is 100um to the side of the trace, but what is the width of the trace for this calculation? Let’s assume it is 1oz copper on this board, then the thickness of the copper is 35um. What is the FOM for this case: FOM = W / G = 35 / 100 = 0.35. When we look at the two figures we’ve calculated, 2 is much bigger than 0.35 so in this case the plane 50um below dominates the impedance, but the traces at the side of our trace of interest also play a part, but only a small part in the impedance. There will be a displacement current flowing right underneath the signal trace, but there will also be a tiny displacement current flowing in the adjacent signal trace (as we don’t usually want this, we refer to it as crosstalk). It follows that trace impedance is therefore determined by the plane, and fractionally lowered by the nearby trace on the same layer.

Can the trace have an impedance with respect to another layer that is further down in the layer stack? No (not really). Assuming that the trace of interest is on the top layer, that the next layer down is a 0V plane, and the next layer below that is a 3.3V plane; then the signal “sees” the 0V plane, but the 3.3V plane is “not in sight” and the top layer trace induces no significant displacement current in it. It might be thought that the induced flow of current in the 0V plane would therefore induce further currents lower down in the stack-up, but this is not the case. The mutual inductance lowers the impedance of the side of the copper in the plane that is next to the trace on the top layer, so the displacement current flows preferentially in the top side of the copper plane - even though the plane may be just 18um thick. There will be a very tiny flow in the copper of the 0V plane that is facing the 3.3V plane, and this will induce a very tiny current in the 3.3V plane, but for all practical purposes we can ignore this.

From this we see that the top layer signals induce currents in adjacent metal in any direction, but the dominant effect is that of the closest metal. If this metal is not at a voltage used by the driver, the displacement currents will still be induced in this layer, but you are now depending on capacitance to link the induced currents back to the place where they are needed. This is a good prescription for creating EMI problems.

The second question about the case when the adjacent copper layer is not a continuous plane you can now work out. The displacement currents become disjointed and need to find a way to get back to where they need to be, but some of that energy is simply not going to get there, it will radiate as EMI. At frequencies up to around 10 MHz capacitors can link different planes together from an AC point of view, if they are sensibly placed. The problem you can’t avoid is that it is not the frequency at which you are switching the signal that matters, but the rise and fall times that are going to determine how much is not likely to be effectively coupled back to the right plane and which is going to show up as EMI in the test lab. Hence why the best advice about splitting your reference plane comes down to one word: don’t.

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