For an 8-layer PCB with strict impedance control requirements on a sensitive net, the signal layer is sandwiched between a ground plane and a power plane.
My question is, will the capacitive coupling between these planes affect the impedance of the signal? Additionally, is it generally better to route high-speed signals on internal layers, or should I keep them on outer layers with a solid ground plane underneath?
Yes, the proximity of both planes will influence the impedance of the signal. It’s not wrong to use a power plane as a reference plane, provided certain precautions are taken.
Routing impedance-controlled traces between two planes is commonly referred to as a stripline configuration. This can either be symmetric, where the trace is equidistant from both reference planes, or asymmetric, where the distances vary.
However, when using a power plane and a ground plane as reference planes in a stripline setup, it is crucial to ensure that the power plane is effectively decoupled to the ground plane. This is typically achieved by placing sufficient decoupling capacitors between the planes to maintain a stable reference and minimize noise.
Yes, the presence of both planes will influence the characteristic impedance (Zo) of your trace due to the additional capacitive coupling. This is normal in a stripline configuration, where the signal is routed between two reference planes.
Both internal and outer layer routing can work effectively. If you opt for an inner layer, you’ll need to adjust the trace width (typically narrowing it) to compensate for the coupling with the additional plane. Tools for impedance calculation can help you determine the optimal width to maintain your desired Zo.
Inner layer offers better shielding from external noise and EMI, making it ideal for sensitive or high-speed signals. Conversely, routing on an outer layer can simplify impedance control as it involves a single reference plane, but it exposes the trace to more environmental factors. Ultimately, the choice depends on your design constraints and priorities, such as noise immunity, manufacturability, and ease of tuning the impedance.
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There are two good replies already given, and there is no need to repeat what they have said. However, there are a few other considerations that are worth thinking through earlier rather than later as they affect your design as a whole.
Let’s envisage what the stack-up could look like (though you said there are eight layers in your board, we’ll simplify things a little by just looking at the top four layers, after all, this is going to be symmetric). Suppose your signal arrives through a surface mounted connector placed on the top side of the board, your signal thus starts on the top layer which can be called Layer 1. The original description says there will be a GND plane so let’s make that Layer 2, an inner signal layer, Layer 3, and a power plane, Layer 4 (which is at the middle of the stack up).
The impedance controlled signal is on layer 1, and as it propagates induces a displacement current on layer 2 (GND plane). Next the requirement is to bring it into the PCB, so you add a via and take the signal down to layer 3. While on layer 3, the signal induces displacement currents in both adjacent layers (2 and 4). Because there is now a displacement current flowing in layer 4, it must be linked to layer 2 using a capacitor, and this must be located as close as possible to the signal via. This is mandatory since the displacement current that had been entirely in layer 2 prior to the signal transitioning to layer 3 is now split with part travelling in layer 2 and the rest in layer 4, but since layer 2 and 4 are not the same voltage, then a capacitor has to be used to link them.
It has already been mentioned that the stripline you have on layer 3 can be symmetric or asymmetric, and here’s where it makes a difference. Suppose you make it symmetric, equal displacement currents will be induced in both planes, but those in layer 4 have to be linked back to layer 2 through a capacitor which is therefore a less than ideal link. To make this work well, you want to offset the position of layer 3 to makes it as close to layer 2 as you can get it. Doing this results in the influence of layer 2 dominating and the current in layer 4 will be much lower. This makes the influence of the GND-Power layer decoupling capacitors at the signal via transitions much less critical. You can get an indication of how much difference this makes by using a field solver to show you the impedance of the stripline and compare it with that of a “buried microstrip” track (i.e., a stripline but with one copper plane removed).
A further matter for consideration is the via that links the signal between layers 1 and 3. The question you need to ask is how is this to be implemented? To these there are a number of possible answers, but here we’ll look at three. Option 1, through via from layer 1 to layer 8: if you are to choose this, remember that the portion of the via between layer 3 and layer 8 is a stub and this will cause signal cancellation at 1/4 wavelength of the length between layers 3 and 8. Whether this matters depends on the frequency range you want to use. Do the maths so you don’t get a nasty surprise. Option 2, same as option 1 but back-drill the via to remove as much of the via stub as possible: this is commonly done and works well by pushing the frequency of the suck-out much higher and so it does not impact the frequency range of interest. Option 3, use two stacked (or very closely spaced) microvias, or a skip-via (i.e., a microvia that goes straight from layer 1 to layer 3). This does not have a stub and should give the best performance. Whichever one you choose, also remember that vias have impedance, and this impedance is also affected by whether you have pads on layers that are not being connected to or whether you remove these pads. When you get it right, the vias become transparent from an impedance point of view (but this does not stop the reflections of options 1 and 2 listed above). Option 1 is the cheapest, but the other two may not be much more in price, you need to talk to your supplier to answer that one.
Finally, routing high-speed signals on outer layers (microstrip), or inner layers (stripline)? Each has its own set of advantages and disadvantages. Many high-speed signals are not individual but are part of a larger group, for example DDRx data signals are often in groups of 32/64/128 bits, but these are usually split into sub groups that are 8 bits wide (plus data strobes). You can route these on outer layers or inner layers but if you have a mixture of outer and inner there are rules to follow associated with the fact that inner layers have a slower propagation velocity (usually around 0.5 * c) whereas outer layers are faster (approx. 0.65 * c). In the case of DDRx, each byte lane (and strobes) need to be flight-time matched, which is hard to do if they are split between outer and inner layers. Higher speed signals usually appreciate layer changes less, so USB and PCIe, etc interfaces are better kept on one layer (which is almost certain to be an outer layer) if possible. It is always the case that they should be adjacent to solid planes. If your eight layer stackup is expecting to split the power plane on layer 4, make sure that no high-speed signals on layer 3 cross the split. Even if the GND plane on layer 2 is solid, the layer 3 signal induces displacement currents in both layers 2 and 4, so splits in layer 4 that are crossed by signals in layer 3 should be avoided.
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If I’ve correctly understood @steve.carney on other threads, then there is also controlled-depth drilling, which is an improvement on thru-hole + backdrill, and might add surprisingly little cost at Sierra.
Back to the original question – were you also asking whether the plane capacitance between the power and ground planes will interfere with signals on a signal layer between them?
I think Rick Hartley youtube videos have cautioned against putting signals between a power plane and its ground for that very reason, but I don’t know whether it is a serious problem vs a “when every little bit matters, remember this too” item.
Controlled-depth drilling typically refers to creating a blind via and connecting specific layers. Controlled depth holes are normally plated. Back-drill refers to drilling out the plating in a through hole to break connections and/or get rid of unwanted copper. It’s a bit confusing as both use the depth control function on the drill machines but have opposite end results. The cost can vary quite a bit as there are several types of tools used depending on the desired result and some of these are fairly expensive and can’t be repointed. How the holes get finished – plated, fill plated, paste filled, resin filled, no fill, etc. – will also effect cost.
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