In a scenario where all critical ICs are located on the top layer, which stack-up configuration would be more advantageous?
Option A:
1 - Signal
2 - GND
3 - Power
4 - Signal
5 - GND
6 – Signal
Option B:
1 - Signal
2 - GND
3 - Signal
4 - Power
5 - GND
6 – Signal
Should the power plane be positioned closer to the top layer (where the important ICs are) or closer to the bottom layer?
The first one might be marginally better. Since both types have ground immediately adjacent the difference would be very small I think, but in theory anything that reduces power supply or ground impedance would be beneficial.
It depends on what aspect of the ICs is considered critcal and where each IC’s power pin caps are located.
For signal type ICs, PWR layer will benefit from being closer which ever half of the stackup that IC localized power pin caps are located (shortest path to provide energy between PWR source through PWR layer to caps then to IC loads). Response time between caps and IC can be quite fast and demanding. Power sources tend to be much slower in comparison to power pin caps.
A common approach for achieving impedance-controlled traces on a 6-layer PCB involves utilizing layers 1 and 6 for the controlled traces and layers 2 and 5 as corresponding ground planes. The choice of power layer (3 or 4) is less critical, but opting for layer 3 may offer slight proximity advantages to key components.
It’s crucial to pay close attention to the layers containing traces 1-2 and 5-6 during stack-up design. While vias can pose potential issues in signal paths, they can be engineered to match the desired impedance, particularly when they span from the top to the bottom layer, avoiding stub-related problems.
Incorporating ground vias between layers 2 and 5 near signal vias traversing layers 1 and 6 can effectively address the challenge of switching reference planes.
Additionally, in certain scenarios, a 4-layer board with a ground plane as one reference layer and a supply plane as the other may suffice. While direct stitching of reference planes with vias isn’t feasible, they can be linked via capacitors.
Regarding impedance-controlled signals on layers 1 and 3 with ground and supply/ground on layers 2 and 4, it’s essential to design signals on layer 3 considering both layers 2 and 4 as references. Achieving impedance control for layers 2 and 3 is more challenging than for layers 1 and 2 due to the difference in sheet configuration, necessitating distinct geometries for layer 3 signals.