In my 4-layer PCB design with the layer stack SIG-GND-PWR-SIG, I’ve been considering the behavior of return currents and electromagnetic fields, particularly when routing signals on the bottom layer.
When routing signals exclusively on the top signal layer, the high-frequency signals have a GND reference plane underneath, facilitating return currents and containing the electromagnetic fields. However, when transitioning from the top to the bottom layer, what happens to the return currents and fields?
Given that the return currents tend to follow the trace path, they likely seek the nearest via to the ground plane and continue along the trace path. However, with the power (PWR) plane situated between the signal and ground planes, there’s a disruption in the coupling of fields to the ground plane. How do the return currents behave in this scenario? Do they disperse throughout the ground plane, or is there another mechanism at play when routing signals on the bottom layer of a 4-layer stack?
If you ensure effective decoupling between the power and the ground planes, the impedance between them remains minimal at high frequencies. Consequently, your high-frequency signal won’t distinguish between the ground and power planes.
If you have placed ground vias in the proper places, the current will flow nicely from top to bottom. If not, then it will follow the shortest path. The power plane may act as a reference also if they are properly coupled with the ground plane.
This diagram illustrates how the return current behaves during layer transitions in PCBs:
When the source current passes through a VIA and loses a low-inductance path, the return current follows the source current along the bottom plane to the VIA, then transfers to the top of the same plane via its side edge (due to the skin effect). From there, it must find a path to connect to the new reference plane for the top signal layer. The return current expands radially until it locates a low-inductance path to couple with the new reference plane.
In scenarios where the top and bottom reference planes have different potentials, they need to be capacitively coupled. This typically occurs naturally as good capacitive coupling is essential for proper power delivery across the PCB. Embedded capacitance throughout the PCB and nearby capacitors assist in coupling the return current through capacitive paths. To optimize this process, it’s recommended to place stitching capacitors near the transition VIA to provide a nearby capacitive path for the return current. However, VIA connections inherently have some inductance, limiting their effectiveness at higher frequencies. Therefore, using multiple stitching capacitors can help mitigate this issue.
In cases where both reference planes are at the same potential (e.g., both ground or the same power plane), VIAs can establish a direct copper path. These VIAs should be strategically placed near the transition VIA, and an array of stitching VIAs should generally connect two planes of the same net throughout.
Once the current reaches the top reference plane, it must travel to the top side of that plane along the board edge, often via stitching VIAs or other transition points.
However, neither solution is perfect. Any layer transition introduces a notable change in characteristic impedance, which can emit high-frequency (HF) energy. This emission can affect the performance of your own circuit (e.g., signal quality degradation, coupling to nearby signals) and nearby signals (e.g., failing radiated emissions compliance tests).
Consider these options:
Reduce HF content (slower slew rate, lower data rate, filtering).
Route on a single layer if possible.
Transition between layers with the same reference plane.
Use stitching VIAs when changing layers with the same reference plane.
Place low-inductance stitching capacitors nearby when changing reference planes.
By understanding and addressing these return current behaviors, you can improve signal integrity and reduce EMI in your PCB designs.
