Ground Pouring Strategy for 4-Layer PCB Design

In my 4-layer PCB design featuring the SIGNAL/GND/POWER/SIGNAL stackup, I’ve opted against pouring ground-connected copper on the top and bottom signal layers. Since, I’ve come across suggestion, that adding ground on these external signal layers, while having a dedicated ground plane layer, may offer little benefit and could potentially lead to EMI issues.

However, I’m encountering a dilemma regarding my I2S traces operating at approximately 12 MHz and the SD card interface traces running at 50 MHz. Given the short rise times of these signals, it’s likely that they will seek the trace path for their return current rather than the shortest path.

Moreover, some of these signals traverse vias between the two signal layers. During layer transition, the return current is expected to seek the nearest path to the reference plane, such as the closest capacitor ground via or MCU ground pin via. This raises concerns about the formation of ground loops, particularly as my board is audio-oriented, and any induced “hum” sound in the audio output would be undesirable.

One potential solution I’m considering is pouring copper connected to the ground plane on the top and bottom layers, supplemented by strategically placed ground vias within this copper pour area. This approach aims to facilitate short paths to ground across the top and bottom layers, thereby reducing the size of ground loops. However, there are concerns regarding whether this copper pour could exacerbate EMI issues by acting as an antenna.

So, the question is: Should I proceed with pouring ground on the top and bottom layers, or would it be advisable to refrain from doing so?

Every board is different, but me, I’d pour.

the return current of conductor on TOP will flow in the L#2-GND
the return current of conductor on BOT will flow in th L#3-VCC
So the return on VCC will join return current on GND thru Capacitor or stray Capacitance
So: 1) add VCC copper polygon on Top to get Capacitance with L#2 GND and add GND copper polygon on L#4
2) add couple of Capacitors 1uF+100nF on 4 corners of the PCB
3) add Guard traces with via fence to GND for Hi Speed Digital Signals and Cloks.

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If you want to use VIAs to cross a signal from Top layer to Bottom layer, and this signal is “high data rate”, then I would say the intermediate layers should be ground. This is the only way to guaranty the return path uses the shortest path (minimum inductance). You should add at least two ground VIAS per signal VIA. Eric Bogatin explains this case in a video

On the other side keep in mind a VCC plane is not a must, You can distribute VCC over the Top and bottom layer without any degradation. Of course if it is very crowded and there are multiples signal crossing Top and Bottom maybe you should consider 6 or 8 layers construction.

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Keep in mind that audio signals and digital signals generally require special considerations to minimize the interaction between them. It is not something that a paragraph can explain.

That said, EMI issues usually improve when copper pours are added correctly so I would not let some vague concept of something that might happen prevent you from adding pours that usually help more than they hinder. As with any rule of thumb, you need to understand the basis behind them so you can decide how and when to apply them.

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@eduado.mateos has identified the critical issue. The first thing to do is correct the layer stack-up. Change it to Sig-GND-GND-Sig and route the power on the signal layers will make the biggest improvement.

Signal layer changes for the signals with fast edges are now trivial. Next to your signal via, place one or two GND stitching vias for the return current. The fact that just about all the energy is travelling in the space between the signal trace and the adjacent GND plane is great because you know where it is. When you have a GND plane and a PWR plane you now have to link them with a capacitor, but the energy spreads out as it cannot “see” where it needs to go, and that which doesn’t find the vias and your capacitor is what the EMC test antenna will see.

When you have routed the power on the same layers as the signal, these traces can be widened out using copper pours. If they are the same voltage on the top and bottom layers, you can link them together with vias, but it isn’t too much of an issue if you don’t.

There is one other thing you need to consider, and that is what the separation distances need to be between the four layers of your board. If you want to keep the displacement current (better name for the return current) tightly constrained in the GND plane adjacent to the signal, then you must keep the separation as small as you can sensibly make it. The best plan is to try to get this separation down to something like 50-100um between Sig-GND layers. As the board should be symmetric, this same figure should be used between GND-Sig also. Therefore it follows that for a typical 1.6mm thickness board, the GND-GND separation will be something like 1200um depending on copper thickness. The critical bit is the Sig-GND distance as this plays the biggest part in making your board be quiet and not an EMI disaster.

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Pouring ground on both top and bottom layers of a PCB is generally beneficial and unlikely to cause EMI problems, provided you follow some best practices:

  • Avoid large, unconnected islands of ground copper. Always use vias to connect your ground pour to the main ground plane. If certain sections can’t be stitched with vias, it’s better to remove those sections.
  • For boards with significant unused space, copper pours can be advantageous with minimal drawbacks.
  • Add copper pours as a final step in your design process. Modifying the PCB layout after adding pours can be challenging and may require removing them temporarily.

Regarding layer changes and high-speed signals:

  • Route high-speed signals close to a plane layer (either ground or VCC), which serves as the reference plane.
  • When a signal changes layers on a four-layer board (changing reference planes), place small ceramic capacitors near these transition points. These capacitors, connected between the two reference planes, ensure a low-impedance AC current path.
  • While reference plane changes are common and generally not problematic, some high-speed buses (like DDR) may have specific routing requirements.
  • Coupling between copper traces and surrounding ground copper on the same layer is relatively weak compared to coupling with an adjacent plane layer.

In summary, adding ground pours to top and bottom layers typically has a positive impact on signal integrity and can help minimize radiated emissions. However, always follow best practices and consider the specific requirements of your design.

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