I’m designing a 4-layer PCB where the internal layers are dedicated to power and ground planes, while the outer layers are for signal routing. Should I fill the outer signal layers with copper pours, or leave them mostly empty aside from the signal traces?
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I add copper where ever I can, as long as it does not have any negative impact on the electrical performance. My practice of adding copper can have a negative impact on getting parts soldered to the board. There is a good balance to find in all designs.
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I have always seen a benefit in adding ground pours. The only significant or potential problem I’ve run into is don’t get them too close to your HF signals as they will capacitively load the line and increase insertion loss.
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In the past, covering all layers with copper pours was a common practice to optimize the etching process during PCB manufacturing. Maintaining a consistent amount of copper throughout the board aided in achieving uniform etching results.
However, modern practices have evolved, and pouring copper on all layers is no longer necessary. Pouring copper on the outer layers doesn’t automatically enhance shielding or impedance control, which are crucial considerations in PCB design.
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In most cases, ground pours on layers other than the ground plane aren’t necessary. However, there’s an exception when utilizing surface-mount (SMT) power devices, and even some through-hole components, that dissipate heat through the PCB. In such scenarios, having a substantial copper area directly beneath the device can prove highly beneficial.
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If EMC matters, it is much better to make both of the two inner layers to be GND, and route the power on the signal layers. When you use copper pours on the signal layers they will now be to lower the impedance of the Power tracks. The reason why you want the two planes to be GND is because this is where the displacement currents from your signals flow. If your signals never change layer (top to bottom, or vice versa) it makes no difference what voltage is present on the plane, but the moment you switch between top and bottom layers it does matter.
To show you why it matters, suppose the plane on layer 2 is GND, the plane on layer 3 is VCC and the signal starts on layer 1 (top layer). When you want to move it to layer 4 (bottom layer) you just put in a via. But the displacement current that was in the layer 2 GND plane has to couple through to layer 3 VCC. But you can’t use a via to do this because they are not the same voltage. Your solution becomes having to put a VCC/GND capacitor at this point. This is at best a poor compromise because things like a standard 100nF 0402 capacitor become governed by their parasitic inductance above a few 10’s MHz, so above 100 MHz or so, the effects of your capacitor are mostly irrelevant. The result of this will be that the signals above this frequency will tend to radiate, and that makes EMC compliance harder to achieve.
Of course, if both planes are GND, they are the same voltage, so where you change your signal between top and bottom layers with a via, you just put a via right next to your signal via, but this one links the two GND planes at this point. Now the displacement current can follow the signal through the adjacent via to the other plane. Problem solved.
The one other thing that goes with this is your stack-up. To minimise radiation off a track, you need to maximise the coupling between track and plane. To do this, you want to reduce the separation between them. On a typical 1600um (62mils) board, if you can make the layer 1 (top) to layer 2 (GND) separation somewhere around 75-150um, and do the same for layer 3 (GND) to layer 4 (bottom), this comes close to ideal for a 4 layer PCB (the Sierra guys will be able to help you with what’s possible).
The proximity of layers 1 and 2 (and likewise 3 to 4) gives you one other big benefit. The capacitance between your copper pours on the outer layers with respect to the nearest plane layer goes up with the reciprocal of the separation distance. In other words, you get more “free” decoupling between power and GND. While the total capacitance is gives you may not be all that big, it is the only capacitance that is not affected by parasitic inductance at frequencies into the GHz arena.
Hence your best policy is …
Layer 1: signals and routed power.
Layer 2: GND
Layer 3: GND
Layer 4: signals and routed power.
And wherever you pass a signal between layers 1 and 4, make sure there is a GND stitching via next to it (or at least somewhere not far away).
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