Return Current Path in High-Speed PCB Designs

Hi, I’m working on a high-speed PCB design and have a question about the return current path for the signal. It’s widely acknowledged that high-speed signals create a return current path on the plane directly beneath their PCB trace.
Consider a 4-layer stack-up with the following layers: Signal (SIG) - Ground (GND) - Power (PWR) - Signal (SIG), and the dielectrics used are CORE - PREPREG - CORE, respectively. In this setup, the core has copper filled on both sides of the dielectric, while the prepreg is a dielectric material without copper on either side.
My question is: Why wouldn’t the return current flow on the top side of the CORE between the SIG and GND layers, given that there is a full copper plane on the top side of the CORE layer?

Not sure if I’m getting your scenario here. If copper layer 1is the topside and the top of the core, and copper layer 2 is ground and the bottom of the core; then the main path (forward path) is on the top and the return current would indeed be on the other side of the core.

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I am unsure what you are saying here as the initial set would have plating issues and cause the two cores to bow. The build would normally be 0.5oz foil | prepreg | 1oz copper | core | 1oz copper | prepreg | 0.5oz copper foil. This allows additional 0.5oz copper over plating to connect down hole and you finish will be 1oz outer and 1oz inner copper (balanced, not bowed)

Hi, as the other contributors have said, the question is a little ambiguous. If you mean that the top signal layer has a GND fill resulting in all signals having GND fills at the sides in addition to GND in the plane below, then the answer is that there will be return currents in the GND fills as well as in the plane below. But the issue is one of how much energy is coupled into which copper. In most realistic PCBs the coupling between signal (layer 1) and GND plane (layer 2) dominates and the coupling between signal (layer 1) and GND fills (also layer 1) is a secondary effect.

It follows that the majority of the return current for the bottom layer (layer 4) must therefore flow in the PWR plane (layer 3). There will also be small return currents in the GND fills on layer 4, but they are largely irrelevant. This arrangement is alright as long as you don’t want to push the signal through a via and route part of it on the top layer (layer 1) because it is now referencing the GND plane. When this happens the return current needs a path from the PWR plane to the GND plane. As a minimum, this requires two vias and a capacitor, which is less than ideal, and is worse than you might think because of the additional parasitic inductance of the capacitor and associated tracks.

The best solution is usually to change your stack-up layers to be SIG - GND - GND - SIG, and route the power on the signal layers as wider tracks. If the currents in your board are too high for this to be possible, you are better off changing to a 6 layer stack-up and putting the power planes right in the middle. This way, when you need to use a via to change from top layer to bottom layer, all you need to do to complete the return current path is place a GND stitching via close to the signal via. This is a big improvement over via-capacitor-via that your present PCB stack-up requires. Obviously, if you are handling very high frequencies you might need more than one GND stitching via, but this is getting into a bigger discussion.

Final point, reading between the lines, you speak of the Core and Prepreg materials as though they behave differently in the presence of EM fields. There are differences, but in reality these are very small. What is more important is their thicknesses because that defines how close the SIG layers are to the Plane layers. It is possible to get thick prepregs, but this is not usually the way things are done. They tend to be thin. Cores can be thin, but tend to be more common in thicker sizes. So if you have not told your PCB vendor what thicknesses you want the materials to be (say if you only specify the thickness of the overall board), you could get any combination that gives the overall figure. So if you ask for Core-Prepreg-Core and say that you want a 1.6mm (0.062") overall thickness, you are more likely to get two 0.5mm cores and about 0.5-0.6mm (approx.) stack of prepregs in the middle. Such a large distance from SIG to PLANE (PWR or GND) means that you will have stronger lateral coupling into the GND fills on the SIG layers, but this is not a good plan because it means that there must also be strong EM fields all around the conductors on the SIG layers which hurts your EMC performance.

Alternatively, if you had asked for Prepreg-Core-Prepreg you would probably find that the PCB house would give you a core that is 1.3mm thick and two prepregs that are about 0.1-0.15mm thick. This means there is strong coupling between SIG and PLANE layers, so the lateral coupling is much lower, and the radiated fields are lower too. It also makes it much easier to create controlled impedance structures (say 50 ohms tracks, or 90 Ohms diff pairs for USB, or 100 ohms diff pairs for Ethernet) can now be done with track widths that are sensible. If you haven’t specified the core and prepreg thickness, you have no idea what track impedances you will have. It also affects EMC strongly and this means that different fabricators could produce boards where one easily passes EMC tests, and the other fails badly, though both are from the same artwork. If you do not specify these thicknesses, you have no-one to blame but yourself if you have poor batch to batch consistency and unpredictable EMC behaviour.


Thank you, Jonathan, for your response. Your answer in the first paragraph addressed my question perfectly, clarifying exactly what I wanted to ask. The additional information you provided is highly valuable, and I will certainly consider it during the design process. Thank You all.

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So you’ve got a couple of misconceptions about how boards are made. And maybe a preconception about the physics.

First, for a four layer board – the stack would be Foil->Prepreg->Core->Prepreg->Foil – Still four layers, but it changes the geometry by a lot. Cores are often much thicker than prepreg (You can purchase them in any thickness you want, but the more common is thick core + thin prepreg). And maybe the prepreg is only 0.1 mm thick compared to the core’s 1.2mm thickness. 1█2████3█4

You want layers 1 & 4 to be mixed power/signal, and layers 2 &3 to be ground reference.

The “energy” of a circuit flows in the prepreg. Charges on the surface of a conductor change speed, which causes a change in dielectric polarization, and that change in polarization causes charges to accelerate in a nearby conductor. It’s called a displacement current. The effects depend on rate of change and distance. You’re right that the energy travels between the bottom of layer 1 and the top of layer 2. We see the effects of that energy transfer as a displacement current in layer 2.

Imagine we made PCBs out of steel instead of copper. And imagine you are an ant carrying a magnet along every trace in your board. You should be able to walk that magnet along every inch of every trace in your design from one end to the other and not have any sudden changes in direction or magnitude of pull force. If you have to cross another trace, that’s going to cause an unexpected jump – no good. if you have to cross reference planes, that’s definitely going to cause an unexpected jump – no good, etc… The only thing beneath a signal trace should be a bit of copper.

All that said, if you can make your circuit work on a solderless breadboard, it doesn’t really matter how you route your board, it won’t matter, you’re not dealing with high enough speeds to care.

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