Ask Me Anything with Atar Mittal

Log in and ask your questions about high-speed PCB design!

Ask me your high-speed design questions below.

For high-speed signals with a typical (good) PCB design, the return path will be tightly coupled to the forward path, usually on the ground plane. On the transmission line level, when the signal first starts propagating, there is immediately a return current up to the wavefront, though capacitive coupling. My question is, what if you route poorly and the forward path is deliberately far from the return path? As the wavefront is propagating down the transmission line, where is the return current for the initial propagation?

What are the critical DRC aspects to watch out for when it comes to designing high-speed PCBs?

Hi Atar,
Could you please share your insights on material selection for high-speed PCBs? How do you balance the demands of signal integrity and cost-effectiveness?

What are your go-to high-speed PCB routing strategies to ensure the highest signal integrity?

Hi Atar, what are some common design mistakes that lead to crosstalk in high-speed PCBs?

What simulation and modeling tools do you recommend for predicting signal performance?

How do you ensure the efficient transition of a high-speed signal from one signal layer to another? Can you share some best practices to achieve this in designs with stringent impedance requirements?

Are there any specific ground plane and return path considerations when you’re modeling a HDI circuit board operating at high frequencies?

I’m not sure how to answer this question but as the signal propagates on the transmission line, it sees an instantaneous impedance each step along the way.

As the signal travels down a uniform transmission line, there is a constant current associated with the signal that successively charges up each section of the transmission line in order to leave a 1V signal in its wake.

The return current is propagating from the load at the same time as the forward current propagating from the source.

I hope that helps.

The two most important things you need to watch out for when designing for high speed are impedance control and type and placement of vias. Make sure that you are maintaining your impedance while routing.

When it comes to material selection for high-speed, results are unfortunately often driven by cost. It’s a tradeoff, if you use cheaper materials, your board might not function as intended and your SI will be impaired.

You can find more info in our High-Speed Material Design Guide: High-Speed Material Design Guide | Sierra Circuits

To ensure high signal integrity in high-speed PCB designs:

  1. Maintain matched trace lengths for differential pairs.
  2. Control impedance and use proper termination techniques.
  3. Keep sensitive signals away from high-speed or noisy traces.
  4. Carefully plan the signal layer stack-up and ground plane layout.
  5. Use serpentine routing to match trace lengths.
  6. Simulate signal behavior and conduct real-world testing.

You can chat with us on our website and ask for a meeting with our design team.

The main trick to avoid crosstalk in your high-speed design is to keep the distance between your signal layer and your reference plane to a minimum. It keeps the electrical field from radiating. If they are let’s say 10 mils apart, that gives more room for crosstalk.

Thank you! To clarify, my question is exactly about the return current you mentioned. You said it is propagating from the load at the same time as the forward current. But what if the return path is physically very distant from the forward path? The paradigm of the return current simultaneously propagating is usually shown in transmission line theory by capacitive coupling between the forward and return paths. But if the paths are very far apart, the coupling is effectively zero. What happens in that case?

The coupling would indeed be zero but every scenario could be unique. The current will follow the path of the least impedance. It would help if we could see your design to better understand and advise you.

Happy Holden says:

“At high freq. the return path is governed by ‘the lowest inductance’ not ‘the lowest distance or resistance’. So this is usually in a plane following the signal going out, so any ‘obstacle’ like a split in the plane will cause noise and an anomaly/distortion. When modeling, items like this will show up so be mindfull in design about interruptions in the return path. This can be difficult with split planes for multivoltages as in FPGAs.”