Kenneth Wyatt will answer your EMC questions here!
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Does trace shielding block EM radiation effectively? Can you recommend the 2 best methods of shielding?
Are there any specific tools to test for EMC of a circuit board?
I generally implement via stitching to ensure grounding in high-speed designs. Which is the best optimal via-to-via spacing to manage EMI effectively?
What is the effective strategy to suppress EM radiation: placing multiple decoupling capacitors of the same value or various capacitors with different values?
What are your strategies to avoid EMC issues in mixed-signal PCBs?
Are there any specific design considerations to ensure the EMC of 5G and IoT PCBs?
How can we prevent EM radiation from the switching power supply?
What kind of filter should we use to avoid EMI in clock circuits and high-speed components? How should we position the filter near the component?
To split or not to split: What is your opinion on spitting ground planes? Is It true that it can cause impedance variations?
I saw that the placement of high-speed circuits close to the GND plane and low-speed circuits to the power plane was recommended. Do you back this up? Would that truly be necessary for a solid return path?
Sorry, this question is not within the scope of EMC.
Trace shielding can be implemented two way; through use of stripline and by using local shields over sections of the PC board. See: Local Shield Options for Wireless/RF Products | Signal Integrity Journal
I’ve written extensively on PC board characterizations using simple tools, such as near field probes. Please refer to the following:
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My “EMC Troubleshooting Trilogy” books on Amazon (Amazon.com: Kenneth Wyatt: books, biography, latest update)
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Assembling an EMC troubleshooting kit (Assembling an EMC Troubleshooting Kit: Radiated Emissions | Signal Integrity Journal)
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Tektronix application note they kindly had me write (Step by Step EMI Troubleshooting with 4, 5 and 6 Series MSO Oscilloscopes | Tektronix)
For best results via-to-via stitching should be 1/20th wavelength for the highest frequency expected. Generally, this is every 2 cm for 20 dB shielding at 1 GHz. Typically, I recommend a via every 5mm.
Use the same values. See Dr. Eric Bogatin’s article, The Myth of Three Capacitors, here (The Myth of Three Capacitor Values | 2020-03-03 | Signal Integrity Journal)
(1) First, understand how digital signals propagate in PC boards. (2) Use a solid return plane! (3) Another great technique is to use the concept of partitioning noisy and quiet circuits. See my PC board design for low EMI series starting with Part 1 here (Design PCBs for EMI, part 1: How signals move - EDN)
Besides the design of the PC board for low EMI cited previously, I find that on-board DC-DC converters create enough broadband EMI that it affects the receiver sensitivity in wireless and cellular modules. See:
A Three-Step Process for Characterizing Self-Generated Interference for Wireless or IoT Products A Three-Step Process for Characterizing Self-Generated Interference for Wireless or IoT Products | Signal Integrity Journal)
Mitigating Self-Generated Interference for Wireless or IoT Products (Mitigating Self-Generated Interference for Wireless or IoT Products | Signal Integrity Journal)
This is a broad topic. I’ve written on minimizing on-board DC-DC converter EMI, see Ten Tips to Minimize EMI from On-Board DC-DC Converters (Ten Tips to Minimize EMI from On-Board DC-DC Converters | Interference Technology)
If you’re referring to off-line (AC line) converters, then ensure the PC board includes a solid return plane as one layer (usually layer 2). Make sure any line filters are located right at the AC line ingress.
The best and simplest is to insert a 1k resistor in series with the clock trace. This, and the parasitic capacitance of the board will help roll off the rise/fall times of the clock.
You should also minimize the length of the clock trace and ensure it does not run along board edges or near I/O connectors.