I’m designing a 6-layer PCB, with components on both sides, mostly SMD (about 95%). The design isn’t high-speed; the fastest signals come from an MCU with an 80 MHz internal clock and some digital lines around 48 MHz.
I came across this suggested stack-up for 6-layer boards:
L1: Signal
L2: Ground
L3: Signal
L4: Power
L5: Ground
L6: Signal
This setup minimizes return path disruption by keeping solid ground planes intact. The recommendation is to avoid routing signals through those ground layers to preserve low EMI and controlled return paths.
Here’s my concern: since most of my parts are SMD, I’ll need a lot of vias to connect component grounds to the inner GND layers. That leads to many holes in the board, which could disrupt the ground planes, potentially affect EMI and cost.
To reduce the via count, I’m considering pouring GND on the top and bottom layers as well, and connecting these to the internal GND layers (L2 and L5) using stitching vias. This way, I can ground many SMD components directly without routing to internal layers unless necessary.
However, I’ve read conflicting advice: some sources say extra ground pours on external layers reduce loop area and improve shielding, while others claim they might increase EMI by enlarging current loops, especially if not handled carefully.
My question is it a good idea to add GND pours on the top and bottom layers in addition to having solid internal GND planes? Will this help with EMI and reduce via count or will it actually create larger loop areas and hurt EMI performance?
Generally you will be better off with surface ground copper so I generally pour the unused areas.
Do not be fooled by your thought about reducing GND vias. Properly placed vias are required to shortest return paths. Lengthening the return path reduces the effectiveness of filter capacitors. Also, speed considerations are not determined by clock frequency. Speed is determined by rise time which can be much faster than most realize. It is better to design for much worse than expected conditions than making assumptions and being surprised when the assembly does not perform as expected.
Hi George, I think you will love (but I am absolutely sure you will need) to watch and understand everything from this lecture first:
[LIVE] How to Achieve Proper Grounding - Rick Hartley - Expert Live Training (US)
Spoiler alert: your board is not “low speed”. You have signal bandwidth in the gigahertz range, regardless of your clock frequency. There are many more topics relevant for your design in this lecture, so be sure to watch everything because presentation of good and bad stackups (including 6-layer ones) is an important part of the lecture.
After watching this, you won’t be so far ahead of yourself and hopefully get the best idea on how to tackle your challenge. Please, do tell us what stackup you finally decide to go for.
As a final note, be mindful of copper % imbalance that you have (keep the stackup symmetrical). Today’s computer screens are pretty flat and everything might look flat on your screen, but then get warped when fabricated.
Using lots of ground vias is not a problem, you actually want plenty of them to ensure short, low-impedance return paths. Via count typically doesn’t drive up PCB cost significantly, especially in today’s manufacturing processes. If your fab is charging a lot for vias, you may want to check with other board shops.
Adding ground pours on the top and bottom layers is generally a good practice, but these pours must be well-stitched to the internal ground planes with plenty of vias to prevent creating floating copper islands or poor return paths. Also, in dense SMT designs, many ground connections still need to be routed to internal planes, so ground pours alone won’t eliminate the need for vias. Make sure your stack-up is copper balanced to prevent board warping.
For tight impedance control, consider routing on layers 1, 3, 4, and 6, with GND and PWR on layers 2 and 5. Alternatively, if impedance control isn’t critical for most signals, you could route on layers 1, 2, 5, and 6 and use layers 3 and 4 for solid power and ground planes.
Also, remember that a well-decoupled power plane can serve as an effective AC return path for signal integrity. Lastly, ground pours (surface or internal) can be especially useful in sensitive circuits where you might want to isolate grounds and connect them to the main ground via ferrite beads.
That is a great stack up. All signals are right next to a ground, and so is the power plane. Depending on the exact distances between layers, the worst that can happen is L3 wanting to couple to its power more than to ground. Assuming you can really do all the routing in 3 layers, great! @myrtlee suggested a compromise that gets an extra routing layer at the expense of separating power from ground.
The vias are fine unless they interfere with your routing. Ideally the plane is unbroken and infinite – but stopping at the edge of the board is a very acceptable compromise, and so are connecting vias … You just want to avoid long slots, particularly if signals on the next layer will have to cross them. But the nature of a via means you won’t have a signal right there even in other layers.
Here’s a 6-layer stackup I would go with prefer for SMT-heavy boards around 1.2 mm thickness:
L1: Signal/Power, L2: Solid ground, L3: Signal/Power, L4: Signal/Ground, L5: Solid ground, L6: Signal/Power
The key design philosophy behind this stack is to ensure that every signal and power trace has a nearby reference plane, ideally a solid ground, to maintain a low-impedance return path. This is essential not just for high-speed signals, but for maintaining consistent performance and reducing EMI in general. Return currents don’t “find their way”, they take the path of least impedance, and it’s up to the designer to make that path obvious and intentional.
I avoid routing on the dedicated GND planes (L2 and L5) to keep them continuous and uninterrupted. That helps preserve signal integrity and ensures good reference for all routed layers.
As for using GND pours on the top and bottom layers: they can be very helpful if they’re properly stitched to the internal GND planes. They’re especially useful for decoupling cap placement or shielding purposes near critical components. But they shouldn’t be seen as a way to avoid placing ground vias entirely, you’ll still need them to tie SMT component grounds directly into your internal planes.
Also, maintain copper balance in the stackup to avoid mechanical issues like warping during fabrication. This layout offers routing flexibility while maintaining good return path integrity and EMI performance.