The proposed stack-up would be far from an optimal choice. As has already been stated, symmetry is a requirement for good manufacturability. However the place to start is the requirements of the signals.
LVDS (Here you have not given a hint at the frequency of operation, so I’ll assume low Gbps) is great. It is differential, but being differential does not mean that the displacement currents flow in the other signal. Even on 0.1mm separation from each other, if I assume that the adjacent layer will be a plane (in practice this will be GND, but we’ll see why later) then only 5-10% of the coupling will be signal to signal, the bulk of it, 90-95% will be signal to plane (GND).
Since the statement has already been made that there is not enough routing on the top layer for all the LVDS pairs, it follows that another layer needs to be used. So let’s assume this will be the bottom layer. You now have the top two layers and the bottom two layers defined. All that now leaves are the two layers for 4.3V and 1.8V power.
So the stack-up becomes: Sig (inc. LVDS) - GND - 4.3V plane - 1.8V plane - GND - Sig (inc. LVDS).
Now let’s put some numbers in, because these will make a measureable difference in overall board performance. First, you want strong coupling between the LVDS signals (and the others too) with respect to the GND plane. So a single prepreg of 50um to 100um is a good choice. As this is quite a small gap, you get good coupling (and therefore reduced fringe fields radiating off the signals, whether differential or singled-ended), and to get the 100 Ohms differential impedance, trace widths of around 100-150um are possible - so good trace density is achieved too.
Next we need to think about the separation between GND plane and 4.3V plane. Here you also want the 4.3V power flow to be tightly coupled to the adjacent GND plane. Close spacing maximises buried capacitance between plane layers (which is great because above about 100-200 MHz, the PCB planes are the only capacitance on the board that works!). So in practice you also want this to be a 50um to 100um prepreg. In addition to maximising the buried capacitance, power to GND proximity defines the mutual inductance between the two layers, and closer is better because the increase in mutual inductance improves the power distribution network impedance strongly. A win-win.
This has not brought us to the centre of the board. The 4.3V plane and 1.8V plane are adjacent to each other. This is not at all what you want because noise on one couples into the other. But as we have seen, if bringing things close improves the coupling, then pulling them apart decreases it. This is easily solved by using a core with about 1mm to 1.2mm thickness (thicker is better). If the Power to GND separation is 50um to 100um, and the Power to Power separation is 1000um to 1200um, it is obvious that the preferential coupling is Power to GND, and the Power to Power coupling is minimised. End result:
Sig (inc. LVDS)
prepreg 50um-100um
GND plane
prepreg 50um-100um
4.3V Power plane
core 1000um-1200um
1.8V Power plane
prepreg 50um-100um
GND plane
prepreg 50um-100um
Sig (inc. LVDS)
A few other things to consider when routing this board:
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If a signal has to change layers, then the displacement currents need to move from one GND plane to the other GND plane. Therefore, if you add a via for signal routing, put in another via to stitch the GND planes together as close as you can to the signal via. This applies to all signals, but especially to high-frequency signals.
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What if the stack-up is changed to route LVDS on inner layers? This can be done, but these signals now reference two layers (above and below), which ideally need to be both GND layers. This is often not feasible and coupling with Power planes is best minimised as much as possible. Also remember that the vias that take the signal from an outer layer to an inner layer will have a stub. If the stub resonance is in the frequency band used by the signal, you are in trouble. You can back drill to remove the stub, or use more esoteric via solutions, but these add cost and complexity. You also need to remember that signal propagation velocity is faster on outer layers (about 65 - 70 % of the speed of light) whereas inner layers are slower (usually around 50 %), so if the LVDS pairs are part of a matched interface, you need to match for Time, not Distance.
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What’s the problem with signals referencing GND on one layer but referencing Power when on another signal layer? If capacitors were perfect and the PCB traces had no inductance, the answer would be nothing. If the signal changes layers, then adding a capacitor with one side connected to GND and the other side connected to Power allows the displacement current to pass through the capacitor and into the other plane. But capacitors are not perfect, they have inductance and this becomes dominant above around 50-200 MHz for most sensible capacitor types. The PCB traces and vias also add inductance which you really don’t want. At low frequencies, this is not such a problem, but if the LVDS data rate is 1 Gbps, the harmonic content will be present at frequencies from 500 MHz upwards. Clearly Power to GND stitching capacitors are practically useless in this range.
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Routing single-ended signals over a GND plane will give you one solution to having a fixed impedance (say 50 Ohms) because we make the assumption that there is nothing else nearby to influence the actual impedance. The same is not true for differential signaling since the other member of the pair is deliberately close by. This has some advantages because it means there is not a single answer to how wide the traces and the trace-to-trace separation need to be, in this case there are a collection of “right” answers. This is good because you can make the traces thinner (and the separation smaller) to get out from a BGA breakout, but once clear of it you can widen the traces if you also widen the separation. If the trace lengths are short this doesn’t matter, but if they have to be longer, wider traces (with the wider separation) reduces signal attenuation, so you may be able to go further if you widen the traces and separation accordingly.
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In the GHz realm, don’t leave things to chance. There are some on-line tools that will tell you trace impedances for single-ended and differential signals, but can you trust them into GHz? The simple answer is why bother, just talk to your PCB supplier and ask them to tell you what the actual impedances will be for the materials used with given traces and finished prepreg thicknesses (i.e. after pressing).