I’m trying to design a PCB using the RTL8211F-CG Ethernet PHY with an RGMII interface, and the datasheet recommends adding a 1.5 to 2.0ns delay to the TX clock (TXC) trace.
The board will use FR4, and I understand the delay is needed for proper timing between the TX clock and data lines — but I’m not sure how to handle this in the layout.
Here’s what I’m looking to understand:
How much trace length (in mm) roughly corresponds to a 2ns delay on FR4?
hi,
I’ll answer your 2nd question first. One way to apply a delay is to add trace length to the existing length to increase the delay of that signal with respect to the signal on another trace.
How much extra length needs to be added is based on that particular application. You will have to know on what layer the traces are routed, outer or inner. The stackup used, PCB material used, Dk of the PCB material etc.
You have specified that you are using a FR4 material. You can check our impedance calculator and calculate the impedance and mainly the propagation delay for that particular trace. This propagation delay is per unit length. Convert it and you will have the extra length you need.
For a typical FR4 material and outer layer trace. You would need at least 12-14 inches, i.e., 30 - 35 cm extra long trace than the other trace. On inner layers, you would need slightly shorter lengths, but still should be 25 - 30 cms longer to achieve the delay of 1.5ns - 2ns
To match this length, you can implement the serpentine routing method in the trace line where this delay is expected
In Kicad 8 you can make use of custom rules. Use constraint “length” to set the rule for max and min length required for a particular net. Find out what is the max length of data signals and add the additional length of 2ns mentioned by Pranav to it and set that as max rule for clock signal. You can use tolerance of 5ns (Calculate its length) to set min value. Kicad DRC should then do its job. Another thing is I was just going through the datasheet and found something related to internal delay. Just check the highlighted section in the attached image. It says that internal 2ns delay can be added by adding a pull up resistor to RXDLY pin.
Just to remember that propagation speed in micro-strip and strip-line are different.
If you use strip-line, Dk you should use is the Dk of the dielectric but if you use micro-strip, then Dk has to be replaced to “Dk effective”. To get this value you need a simulator.
Adding that much delay will require an enormous amount of space to fit in all the extra length you need. It may be worth looking at the data sheet for the MAC that you are driving this with and see if it has any options for adding delays in the MAC (this is sometimes available). It is also worth having a look at any reference design and see what they did there (though the answer may be in software, not hardware).
