Optimizing PCB Stackup and Trace Width for RF Signal Routing

I’m currently working on designing a PCB with 6 layers, and I’d like to discuss a couple of questions regarding the stack-up and trace width optimization for RF signal routing. Here are the details:

  1. Designing for a 50-ohm signal, with only one area of the PCB requiring 50-ohm impedance.
  2. Frequency range: 0.9GHz - 1.6GHz.
  3. 6-layer board with 1oz (35μm) copper on each layer and the same dielectric constant for each layer.
  4. The RF signal will be routed on the top layer, with the ground (GND) layer chosen to optimize trace width.
  5. Going from Layer 1 to Layer 2, I obtain a trace width of approximately 0.22mm.


  1. If I were to cut a region out of Layer 2 so that the GND plane for the RF circuit on the top layer became Layer 3, can I assume the dielectric constant to still be 4.1 if both core/prepreg have Er = 4.1? And therefore, do I just increase the ‘h’ value in the equation for trace width?
  2. Do I need to factor in anything relating to the missing copper on the inner layers, or can I consider that the board will be made so there is no air gap?

I would appreciate any insights on these matters. Thank you!

Yes. For all practical purposes it is and the result should be close enough.

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I don’t know of anything you can do to lower the risk of an air bubble. You should contact your PCB fabricator about this.

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