I’m currently working on designing a PCB with 6 layers, and I’d like to discuss a couple of questions regarding the stack-up and trace width optimization for RF signal routing. Here are the details:
- Designing for a 50-ohm signal, with only one area of the PCB requiring 50-ohm impedance.
- Frequency range: 0.9GHz - 1.6GHz.
- 6-layer board with 1oz (35μm) copper on each layer and the same dielectric constant for each layer.
- The RF signal will be routed on the top layer, with the ground (GND) layer chosen to optimize trace width.
- Going from Layer 1 to Layer 2, I obtain a trace width of approximately 0.22mm.
Questions:
- If I were to cut a region out of Layer 2 so that the GND plane for the RF circuit on the top layer became Layer 3, can I assume the dielectric constant to still be 4.1 if both core/prepreg have Er = 4.1? And therefore, do I just increase the ‘h’ value in the equation for trace width?
- Do I need to factor in anything relating to the missing copper on the inner layers, or can I consider that the board will be made so there is no air gap?
I would appreciate any insights on these matters. Thank you!