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What is the current carrying capacity of 30mil diameter, 10 mil hole size, 39.2 mil height VIA, usig Sierra online calculator, show screenshots for each step taken. Sierra demo video and webinars are very poorly shown for how to use it

Hi Syed, do you mean our Via Current Capacity and Temperature Rise Calculator?

For this, you need to enter your via parameters in order to get your maximum via current capacity.

See here (the order in which you enter the values doesn’t matter but this is how I did it):

I entered your given via height and hole size, then I assumed a 2-mil plating thickness and 20C temperature rise.

See the results.

no, This is not correct. 30mil Dia and 10mil hole gives (30-10=20mil copper). Plating would be 10mil and not 2 mil. or in the case if hole is filled with copper then what would be the answer? Online calculator gives wrong answer because it is based on lookup tables and not design mathematical equations. Therefore, most of the times it would be useless.

How do I determine maximum trace length and what is my trace length goal?

From Track properties in Altium.

Hi Syed,
It seems there’s a misunderstanding regarding the terminology

  1. Definition of Annular Ring: The annular ring is the width of the copper pad around the hole on each layer of the PCB. It is measured from the edge of the drilled hole to the edge of the copper pad. (30mil Dia and 10mil hole gives (30-10=20mil copper) this is your annual ring

  2. Plating Thickness: The plating thickness refers to the thickness of the conductive material (usually copper) deposited on the walls of the drilled hole, which connects the layers of the PCB together.

  3. Filled/Unfilled Vias:
    Filled Via: A via in which the drilled hole is completely filled with conductive material (e.g., copper) for enhanced electrical and thermal properties.
    Unfilled Via: A via in which the drilled hole is left empty or non-conductive, providing a cost-effective solution for simpler PCB designs.

Now If the hole is plated through (meaning it’s filled with copper), the plating thickness would be equal to the hole size, which is 10 mils in this case.
Now for Filled via you can consider it to be a single stranded wire of 30AWG (10 mil thick) of length 39.2 mil long, now you can find out how much current a 10mil thick copper wire can handle, via will handle slightly less then that.

but in non filled vias plating thickess will be
IPC class 2 they do 0.8 mils via platting and IPC class 3 they do 1 mil via plating

i am adding calculation for both

if your looking to share more current

  1. Increase Via Size: Increasing the diameter of the via will decrease its resistance and thus increase its current-carrying capacity. However, this may impact the available space on your PCB and increase costs.
  2. Use Multiple Vias: Distributing the current across multiple vias can reduce the overall resistance and increase the current-carrying capacity of the connection. Placing several vias in parallel can effectively share the current load.
  3. Thicker Plating : Increasing the thickness of the plating inside the hole will reduce resistance and enhance current-carrying capacity. However, this might lead to increased manufacturing costs.
  4. Use copper/conductor filled vias: It wii enhance current-carrying capacity. However, this might lead to increased manufacturing costs.

Via current Capacitor calculator is design based mathematical equations and not lookup tables.
if you can specify in detail your mathematical calculation results or any other tools your are using to conclude to decision that calculator is giving wrong result please share we will analyse from our side and update you.



Thank you for the clarifying examples. They definitely helped, but were so clear that now I’m wondering a few more things.

In your example of a 30 mil diameter ring around a 10 mil hole, you said that left 20 mil for the annular ring. Is it safe to assume that:

(1) The 20 mil of “leftover” diameter would only count as a 10 mil ring, because that 20 has to be split across both sides?

(2) It would actually be a 10.8 mil or 11 mil ring because of the via plating? (Would it still be described as 10, rather than 11? Is this just a significant figures convention, or because drill registration isn’t perfectly centered, or …)

(3) You give four suggestions for carrying more current. You warn that three of them may lead to increased costs. Wouldn’t extra vias also lead to increased costs? Are extra vias cheap (or even free?) compared to thicker plating or larger or copper-filled vias? Is that relative cheapness specific to laser-drilled vias/high speed, or is it a general rule?

(4) You say that a copper-filled via would carry slightly less current than an equivalent gauge wire. Is this because of advantages to the wire-manufacturing process in terms of smoothness? Because of problems at the “bends”? Some other reason I haven’t thought of? Unknown, but empirically observed?

(5) Is the not-quite-a-wire reduced current-carrying capacity of copper fill enough to worry about matching with traces and/or off-board connector wires, or is it still in the “you aren’t paying enough for that to be your problem yet” category, even for high-speed?

Thank you again.

  1. Annular Ring Calculation:
  • The 20 mil “leftover” diameter would indeed be split across both sides, resulting in a 10 mil annular ring on each side.
  1. Effect of Via Plating on Annular Ring:
  • The via plating does add thickness to the annular ring. While it may technically increase the annular ring diameter, it’s common to still refer to it as a 10 mil annular ring for simplicity. The slight increase in diameter due to plating may not always be explicitly accounted for in terminology, but it’s understood in practical PCB design.
  1. Cost Considerations of Extra Vias:
  • You’re correct that adding extra vias can also lead to increased costs, especially if it requires additional drilling processes. The relative cost-effectiveness of extra vias compared to thicker plating or larger/copper-filled vias can vary based on factors like manufacturing techniques, materials, and the specific requirements of the PCB design. It’s not a universal rule, and cost-effectiveness should be evaluated case by case.
  1. Current-Carrying Capacity of Copper-Filled Vias:
  • The slightly lower current-carrying capacity of copper-filled vias compared to equivalent gauge wire may be due to factors such as manufacturing processes, potential irregularities in the filling process, or limitations related to bends or corners in the via structure. The exact reasons may vary and could involve a combination of factors.
  1. Matching Copper Fill Capacity with Traces and Connectors:
  • Whether the reduced capacity of copper-filled vias compared to wires is a concern depends on the specific requirements of the application. For many designs, especially those not operating at extremely high speeds or requiring exceptionally high current densities, the difference may not be significant enough to warrant special considerations. However, in high-speed or high-density applications where every aspect of signal integrity matters, matching capacities between vias, traces, and connectors may be necessary for optimal performance.

Well, you haven’t listed too much info here. Are you building a delay line?