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I will post all the questions asked during the webinar below. Feel free to add more to this thread and tag our @Sierra_Experts.
I would like to know the fabrication method difference of PCB and IC substrate. Thanks
How many GND via should surround a single signal via in a coaxial via structure for impedance matching?
Is there a possibility in the future to reach smaller annular ring for laser vias and mechanical vias like having annular ring around 2 mils and what is min drill diameter that we might be able to reach with both types , since smaller via structures are needed for 224G applications ?
What is the difference of positive and negative etchback?
What is the meaning of ‘controlled depth’ for blind and buried via?
What advantage does positive etchback give in terms of reliability?
What about annular ring of buried vias?
Is there an advantage (cost, etc.) for filling just some vias as opposed to filling all vias?
Which is recommended way to reduce the stubs in high-speed designs?
What’s the best via to plane clearance? What’s the minimum designers can get away with while maintaining good DFM?
How many GND via should surround a single signal via in a coaxial via structure for impedance matching?
Is there any risk of having >10:1 aspect on thru drilled vias?
Recommended spacing for stitching vias?
Putting more via means adding cost, so what would be the optimal number of GND vias to surround one signal via?
How we can judge signal integrity after via design?
How to calculate the aspect ratio of blind and buried vias?
For IC substrate, if the trace and space and vias are smaller, then it would go through more or less the same processes, however, we would use different parameters for the process. Do you have a specific question around a specific process? Some of the variations in process have been named, semi-additive process, for example, where you start with a very thin copper foil. Hope that helps.