@ThePCBGuy will answer your questions on DFM. Start posting now!
What are the most common errors you see when running DFM checks? Are some errors serious enough to cause a board to fail?
Does Sierra have engineers to check for DFM? If so, do you check all boards or just the most complex ones? I think you do assembly too. So you check for DFA too?
Hi Amit, Do you have any guidelines to optimize component placement for manufacturability? How about recommendations to reduce assembly costs?
What tools do you use to check for design errors? And what happens if you spot any? Do you make the necessary changes or do you request the customer to handle it and resend the files?
Can you give some recommendations regarding via drilling? Can you share how you avoid breakouts? And what do you do if the customer requirements aren’t met?
What are the most common 4-layer and 6-layer stackups?
Can you explain why it is preferred to have +3mils/-Hole size for vias? Why the standard +/-3mils for through holes are not used?
How does class 3 change the annular ring spec? If targeting 7mil-8mil annular ring, why would the +/-3mils not conform and require a class 2 designation?
How does the tolerancing change for micro vias?
Hi Julia. Where did you see this?
4 layer is:
1 – signal
2 – ground
3 – power
4 – signal
For 6 layers I would recommend:
1 – signal
2 – ground
3 – power
4 – signal
5 – ground
6 - signal
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We won’t edit your via requirements unless we see that there might be annular breakouts, especially for IPC Class 3/mil-spec boards where breakouts are not allowed. In that case, we will increase the pad size if there is space.
For Class 3, make sure that you leave enough spacing in case we need to increase your pad size to make sure we won’t breakout of the annular ring when we drill your vias.
You can read more here:
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My recommendation would be to avoid placing components too close to each other. That not only makes assembly more complicated but also more costly.
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We check for all jobs and do DFA, too.
We check the customer’s data against our own design rules. This is what we call a DRC check. Our software analyzes the design for potential fab issues. We check signal layers, outer layers, plane layers, signal inner layers, drills, solder mask, copper… If we see that some errors or discrepancies, we let the customer know on our customer portal.
If you have a complex job, we might suggest to run a first article.
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The most common issues we see have to do with annular rings, stubs (as in traces that go nowhere), IPC netlists that don’t match the customer data, via-in-pads that are not requested to be filled, discrepancies of drill tables (as in the drill counting doesn’t match the data provided), drill tolerances…
The list goes on but we have engineering teams who check for these errors specifically so we don’t release a job that can’t be manufactured.
If you work on Class 3 or mil-spec designs, double-check your annular rings and make sure you leave room to avoid breakouts.
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There can be issues in all the board files of the PCB like Silk, Solder mask, Copper layers and drill layers along with missing information in the Fabrication drawing provided.
Here are few of them but not all.
1- Line width spacing not supporting the base copper weight
2- Drill count mismatch between the drill chart and the drill file
3- Missing drill hole tolerances, drill type (via, PTH, NPTH)
4- IPC Netlist not matching with the data
5- Di-electric thicknesses in the stack up not matching to the overall board thickness
6- Annular ring for vias and component holes for class 2 and class 3 orders
7- Missing / Extra Solder mask, Paste features
8- Unterminated traces (Stubs)
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We have a software that we feed with our own manufacturing tolerances. Our engineering teams check your design against our values. If we see any potential issues, we alert you on our customer portal. If it is an issue that will cause the board to fail or make it difficult to manufacture, we will ask you to edit the design.
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Only recommendation would be to use the largest drill size that the pads will allow. Other than that we take care of the rest.
How to avoid breakouts gets complicated but here are the basics:
• Internal layer to layer registration is critical so need a system to accurately predict and measure material movement. Everything shrinks when it goes into the lamination press to varying degrees
• Use Direct Imaging to ensure good front to back image alignment on the cores
• Good control of the Lay-up/Lamination process to ensure proper core alignment.
• Use of X-Ray drill to acquire internal registration and accurately drill targets for Vision drill. The X-ray drill also measures and confirms predicted material movement and automatically updates the system.
• Use of Vision drill which aligns and scales each panel.
• Use a drill room control software system that takes the stack-up data and automatically assigns and loads the drill parameters into the drill machines. Provides process consistency and eliminates operator error.
• Confirm good drill registration using real time X-ray systems.
If a panel doesn’t meet customer requirements it is scrapped and re-made.
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Thanks Steve
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