It depends on the wavelength of the signal. Normally the vias should be spaced by wavelength/10 or 20 so accordingly how much is possible can be added. Also need to keep in mind the planes on internal layers, adding too many vias should not affect the planes on internal layers.
We can do smaller, but the limitation is reliability and meeting IPC spec requirements.
Bottom line is you want positive etchback for high rel applications. Positive etchback is where the dielectric is removed and the copper inner layer is exposed more.
Controlled depth is a function of mechinical drilling. It can be used for either back drill to break layer connections or to limit the number of connected layers. This is similar to laser vias but are typically used for larger diameters and thicker dielectric.
With positive etchback the interconnects protude from the hole wall. This allows the plating to wrap around the interconnects making a 3 point contact which stands up better to Z axis expansino and helps eliminate the separation between the plated copper in the holes and the interconnects.
3 mils recommended for microvias
You can fill only a few vias in your circuit instead of all of them. This approach will lower manufacturing costs and simplify the overall design.
Choose blind vias to minimize via stub length. For through-holes, incorporate backdrilling to remove unnecessary stubs.
The required clearances in PCB designs depend on the material used in the stack-up, whether itâs homogeneous or hybrid. Assuming a homogeneous stack-up with FR-4 material and an aspect ratio of 10:1, for 4, 6, and 8 layers, a 6 mil drill-to-copper clearance is needed. For 8, 10, and 12 layers, a clearance of 7 to 8 mil is necessary. Plane-to-plane spacing varies based on the copper weight; for 1 oz, 5 to 6 mil is preferred, and for half oz, 4 to 5 mil is suitable.
You can choose more than a 10:1 aspect ratio. However, it will increase the design cost, intricacies, and reliability concerns as well.
For low-drequency designs, we recommend incorporating λ/20, and for high-frequency circuits, λ/10 spacing between stitching vias, where λ is the signal operational wavelength.
To minimize via impedance discontinuity, you can opt for a coaxial via structure with a minimum of 2 and a maximum of 4 ground vias surrounding a signal via.
To assess signal integrity after the design phase, you can generate a circuit model with identical parameters and simulate it using a 2D field solver. Inspect eye patterns to gain insights into the designâs performance in the time domain. Additionally, conducting a Bode plot analysis offers an SI evaluation in the frequency domain.
The standard aspect ratio for microvias is 0.75:1.
So âpositive etchbackâ isnât really about how the copper gets etched, it is about etching away substrate from via walls to leave extra copper poking into the via for a better connection?
And it isnât needed for normal PCBs? Is it needed for Class III, or a subtype? Or only for specific individual designs?
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Thatâs correct. Itâs called a three point connection and helps eliminate the separation between the inner layer copper and the via barrel plating caused by excessive thermal expansion and or stress. Itâs mainly a Class 3 Mil Spec requirement and not needed for normal commercial PCBs. It also requires a long Plasma cycle so there is additional cost involved.
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