This is my first time designing a high-speed PCB. I’ve gone through available literature on DDR3 signal routing and put together the following summary to clarify my understanding. I’m sharing this to make sure my understanding is correct—and to find out if I’ve missed anything important.
Signals should be grouped into three categories:
• DQ[0], DQS[0], and DQM
• DQ[1], DQS[1], and DQM
• Address/Command (A/C) signals and clock
Each group should be routed with matched lengths.
Data signals (DQ, DQS, DQM) should be routed on the top layer and length matched within their respective group.
A/C signals should be routed on the bottom layer, and the VTT power plane should form an island on that same layer for proper termination.
In a 6-layer stack-up, the layer directly above the A/C signal layer (i.e., layer 5) should be used as a unified VDD power plane.
Clock differential pairs must avoid intra-pair mismatch — no meanders within the pair.
For length matching, serpentine meanders should be avoided.
Follow the 3W–2W isolation rule for proper signal spacing and crosstalk reduction.
Any feedback or corrections from the community would be greatly appreciated.
All controlled impedance traces (DQ, DQS, DQM, Address, Command, Clock) need to be designed to a specific impedance (typically around 50 ohms single-ended and 100 ohms differential for the clock).
Each needs to be length matched separtely and you can use serpentine meanders.
Between the pairs, you can maintain 5mils for differential pairs.
Maintain unbroken ground reference. These ground planes act as return paths for the signals and are essential for maintaining signal integrity and reducing EMI.
I’ve completed Data Lane 0 and have designed the single-ended 55 Ω and differential 100 Ω DQS traces on Layer 1. According to STM’s guidelines for DDR3 hardware interfaces, data lines should ideally be routed on the top layer. However, due to routing limitations, it’s no longer feasible to keep all data lanes on Layer 1 without introducing vias.
Would it be acceptable to route Data Lane 1 on Layer 3 instead?
For context, here’s my stack-up plan:
Layer 1: Signal data lane 0
Layer 2: Ground
Layer 3: Signal (intended for Data Lane 1) and vref
[Not official advice, just feedback from the community]
From looking at some vendor sites ( https://www.ti.com/lit/an/sprabi1d/sprabi1d.pdf?ts=1746661859714 and AMD Technical Information Portal ) your summary seems to agree reasonably well, except that
(1) they have some additional constraints on total length (latency) and on skew between the three groups. These probably won’t be the binding constraints, but don’t let the address/control group get too far off matching latency with the data. (and apparently if they will be different, address/control should take the longer/slower path, which explains sending it to a farther layer.)
(2) I think the specific layer numbers were more an example than a requirement. For example, I interpreted it as meaning that referencing the Address/Control signals to ground would be even better, but referencing to that power plane instead would still be fine if you have enough capacitance tying the power plane back to ground.
(3) They would like even more isolation (TI mentioned 6W), though I think that was some combination of “more is always better” and “don’t run signals unrelated to DDR3 nearby”
(4) I think the no-serpentine advice was a combination of “keep the differential pairs well matched instead of correcting later with a serpentine in one of the traces” and "don’t serpentine so sharply that the trace has a chance to cross-talk with itself one turn ahead/behind.
Yes you can route one data lane on layer 1 & another data lane on layer 3 and also you have layer 2 & 4 as GND so it will have return path.
While routing on layer 3, trace width and spacing will change. Please take care.
Keep it separate (Vref) from the data signal trace on layer 3 as much as possible to avoid noise coupling.
Try to maintain ground reference for A/C signal under the routing area.
To confirm, I’m planning to route Datalane1 as an embedded stripline to ensure better signal integrity.
I also have a few clarifying questions:
From the layout guidelines, I understand that clearance between signals should ideally be 2S the dielectric thickness (S) to minimize crosstalk. However, in some areas where I’ve added serpentine traces, the spacing drops below 2S.
Should I re-route those sections to maintain the 2S rule even within the serpentine shapes?(CU thickness is 1 oz)
Regarding VREF, if I assign a full plane (e.g., Layer 5) to VDD_DDR, would it be acceptable for VREF to share a small isolated island on that layer? Or should VREF be placed completely separately to avoid noise coupling?
Also, when the guidelines mention VDD_DDR should be unified, does that imply dedicating a complete layer solely to VDD_DDR (i.e., a solid power plane without splits)? I want to confirm this understanding is correct.
Keep in mind that there usually is more than one potential method to route DDR critical signals. Many times, the processor manufacturer has guidelines that explains the options and recommendations. Note that these guides many times are hidden behind security so you usually need to request access.
Beyond that, keep in mind that length matching generally is better if you are matching delay length/time instead of physical length. Where this becomes really important is when you route some nets on outer layers, but other nets for the same group on inner layers. Delay time is different between inner and outer layers and this needs to be compensated for. This is why many recommendations suggest routing all of a group on a single layer in order for physical variences to be applied equally across the complete group. Do not forget that vias also have “length” so make sure your layout tool acounts for that based on signal path, not just overall via length.
Another item to note is that within the processor, each net has internal delay that is unique to the internal configuration. These delays also should be figured into the overall delay calculations in order to increase the accuracy of length matching.
It is best to use solid GND reference layers adjacient to critical signals. Avoid PWR layers for returns and if done anyway, do NOT route over splits/voids and be sure the signals are adjacent to the correct voltage that powers those signals.
I highly recommend Beeker’s “Billion Dollar Mistake” seminar.
One last thought. PCB fabrication has tolerances so the best bet is to length match nets as tight as possible instead of to the largest tolerance allowed by guides. You do NOT want to design at the edge of length tolerances, only to find that PCB fabrication tolerances (which are out of the designer’s control) push the result over the limit.
