I’ve noticed that some processor application notes, like the STM32MP1, claim you can fully fan out BGA packages, including high-speed interfaces like DDR and USB, using just 4–6 layers and minimal HDI (e.g., only L1–L2 microvias, no buried vias). For example, one app note says a 4-layer stackup with signals routed on the outer layers and inner layers reserved for power and ground.
My question is: Is it really a good idea to route high-speed signals like DDR and USB on the outer layers, given the lack of shielding compared to routing them between internal reference planes? I’ve always understood that routing these on internal layers improves signal integrity and EMI performance. So is this approach a practical tradeoff used in real-world designs, or is it mainly a tradeoff made for cost reduction at the expense of performance margin? How much of a concern is external noise or EMI when routing such signals on surface layers?
Routing high-speed signals like DDR and USB on outer layers does come with some design implications, but it’s not without technical advantages. For example, outer-layer traces typically experience slightly lower dielectric losses and faster propagation due to a lower effective dielectric constant—around 160 ps/inch for outer layers vs. 175 ps/inch for inner layers in standard FR-4. This can influence delay matching and should be accounted for when routing signal groups.
Interestingly, having a single adjacent reference plane (as is often the case on surface layers) can simplify impedance control, since you don’t have to balance the spacing between two planes. That said, the lack of shielding compared to internal layers does make outer-layer routing more vulnerable to EMI and crosstalk if not carefully managed.
In practice, this approach is used in cost-sensitive designs where layout is tightly constrained, and performance requirements are within margin. But it requires extra care in layout, such as controlled impedance, tight return paths, and sometimes additional ground stitching vias to contain emissions.
Using a 4-layer board with VCC and GND as the two inner layers is quite common and can offer low-impedance power delivery, which benefits high-speed designs. In this setup, signals on the outer layers have only a single adjacent reference plane, and no nearby second plane or overlying signal layer to help with shielding.
This inherently means those outer-layer signals are more exposed to EMI and environmental noise compared to signals routed on internal layers, which are sandwiched between planes. That said, with proper design techniques, like tightly coupled return paths, good impedance control, and well-placed stitching vias, outer-layer routing can still be reliable in many real-world designs, especially when cost constraints limit layer count or HDI use. So, while it isn’t the most ideal setup for signal integrity, it is a workable compromise in designs where the performance margin allows it.