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How to decide which design files to share with your fabricator (video)
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0
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54
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July 9, 2025
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9-Point PCB Design Checklist for DFM Compliance
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1
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323
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July 8, 2025
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DDR3 Interface Design with STM32MP157FAC1 Using KiCad
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1
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250
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July 3, 2025
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Need Help: DRC Rule Error After Removing severity from the Design Rule – Rules Disappeared
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2
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99
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July 2, 2025
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Optimal 6-Layer Stackup for low-speed SMD-dense boards
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5
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225
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June 30, 2025
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How critical Is control impedance tolerance in short RF traces?
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5
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148
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June 30, 2025
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A Complete Guide to PCB Interfaces and Communication Protocols
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2
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169
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June 25, 2025
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Reference plane requirements for controlled impedance routing
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4
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180
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June 21, 2025
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Trace width guidelines for single-sided PCBs
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7
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235
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June 18, 2025
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Set the right aspect ratio and capture pad
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0
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74
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June 17, 2025
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Dk Variation with temperature in PCB Materials
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6
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228
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June 11, 2025
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CPWG Height Calculation and Ground Clearance for Trace Antennas
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3
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183
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June 2, 2025
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Understanding Staggered Via Transitions in Multilayer HDI Designs
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3
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122
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June 2, 2025
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Backdrilling vs. Blind Vias
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6
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618
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May 30, 2025
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Is My HDI Via Strategy Correct for .5mm FBGA?
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9
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193
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May 30, 2025
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How to Design a PCB Trace Antenna with Limited Datasheet Info?
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1
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99
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May 29, 2025
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Power Plane Limitations and Routing Alternatives in Multilayer PCBs
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2
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120
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May 29, 2025
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Clarifying my understanding of the 8-layer PCB stack up focusing on DDR3, PMIC sequencing, and ground/power plane design
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4
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364
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May 22, 2025
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PCB Material Comparison
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5
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472
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May 21, 2025
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Transition to Halogen-free PCB materials
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5
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171
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May 19, 2025
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DDR3 Address/Command/Clock Length Matching Clarification – Is My Understanding Correct?
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3
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326
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May 13, 2025
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Use of Teardrops in PCB Design
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11
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439
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May 12, 2025
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PCB heat dissipation through air and heatsink
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7
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237
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May 12, 2025
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Difficulty Setting Trace Isolation Due to Close Pad Proximity in KiCad?
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8
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286
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May 12, 2025
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WEBINAR HIGHLIGHT: Maintain Optimum Trace Width and Spacing
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0
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39
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May 12, 2025
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OPEN DISCUSSION: Which PCB design software do you use and why?
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5
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174
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May 12, 2025
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Routing of high-speed signals (DDR, USB) on outer layer
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2
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139
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May 7, 2025
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2-Layer vs. 4-Layer Boards for DDR3
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8
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294
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May 2, 2025
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Learning the DFM process…
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0
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49
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May 1, 2025
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How to Length Match RGMII Data Lines — Meanders Not Forming on Shortest Trace in KiCad
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6
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265
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April 29, 2025
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