Hi everyone,
I’m facing an issue in KiCad where I’ve defined design rules for pad isolation, which allows me to route traces within the footprint. However, when I attempt to route the trace out of the footprint, maintaining the specified net class clearance becomes difficult due to the close proximity of the pads. The trace seems to run into clearance violations as I try to exit the footprint, even though the design rules are set.
Has anyone dealt with a similar challenge? I’d appreciate any tips on how to handle trace routing and clearance when exiting tight footprints in KiCad.
design rule for pad clearance
Thanks for your help!
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what are those two pads are they through pins? why are they not inline? What is the spacing rule set as of now? what type of trace is it? is it a normal signal or some impedance trace? how much current is flowing through it? What is the voltage? How much is the copper thickness? Kindly give all these details to understand what you are trying to do. If you want to reduce the clearance rule in a specific area on PCB, you can define an area and use it to set the rule. An example image is attached. You can change either A type or B type to trace instead of pad, you can also define net class and layer. The reason for asking all above details is because your clearances appear to be too much to me, so want to check whether you really need so much clearance.
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I’m routing RGMII data lines following the manufacturer’s hardware interface guidelines, which recommend using an embedded stripline. In this setup, the 4th and 6th layers are ground planes, and the 5th layer is used for signal routing. The guidelines also require specific isolation rules. Initially, when I applied the isolation rule to the traces, I was unable to route from the pads. To resolve this, I adjusted the design rule specifically for the pad clearances, which allowed routing from the pads. However, when I place a transition via (blind via) on the trace, routing becomes difficult again due to the same clearance constraints.
copper thickness is 1 oz
values from impedance calculator
Thank you for your guidance and time—it’s been very helpful.
I can see as per your new image, you were able to get the trace out between two vias right? What did you change?
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Yes, I lowered the clearance to the trace and then adjusted the required trace width accordingly. That allowed me to route the trace between the two vias successfully
Regarding the rule Clearance between adjacent Pad and Pad of an IC for Power class, do we need to classify certain ICs explicitly as ‘Power class’ to apply this rule? If so, how should we define or mark these ICs in the design so that this DRC condition—especially the intersectsArea('PTP') part—can correctly identify them?
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Kindly ignore the power class name, the rule does not take into consideration the power class. Kicad has an option to define an area on the PCB and name that area. PTP is the area name so all the traces in that particular area will follow the rule defined for that area.
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