Is My HDI Via Strategy Correct for .5mm FBGA?

Dear community,
I’m designing an HDI PCB for .5mm FBGA components and want to verify my via strategy before finalizing the stack-up. Based on what I’ve learned from Sierra Circuits’ HDI design guidelines, I’ve planned the following approach
stack up

I’d like to confirm whether this understanding is correct:

  1. Do I need to include the L7–L8 HDI layers when fan-out is only required on the top layer?”
  2. What are the potential risks of using an 8-layer core (1+8+1) instead of 1+6+1?
  3. From what I understand, it’s common to use FR-4 for the core layers and high-speed materials like Megtron 6 or Isola I-Speed for the outer HDI layers. Is this correct?
  4. Is the via combination shown in the attached screenshot suitable for fan-out in a 1+n+1 HDI stackup? Can this be used instead of through-hole vias?

Any guidance or feedback would be greatly appreciated

If your fanout and routing requirements are fully met on the top layer and possibly L2 (microvias from L1–L2), you technically don’t need deeper layers like L7–L8. But keep in mind that any unused layers still contribute to the overall cost and complexity of the stackup. It’s worth wondering if your deeper layers are necessary for SI.

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I think that’s a common hybrid approach. You can place high speed materials on the top and bottom buildup layers where your signals are routed and keep the inner core as FR4 to manage costs–just a tip. Just check if your fabricator does hybrid. You never know.

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I think that setup is actually ideal. Microvias take up less space than THs and help you escape tight pitch BGAs more efficiently. Now a lot of designers skip through holes entirely. Just make sure the stackup and via strategy match your fab’s cap.

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Going with an 8 layer core can work but it comes with tradeoffs. The thicker core makes the board harder to fab which could lead to lower yields or longer lead times. There’s also a higher risk of warping especially on larger boards. And depending on your via structures reliability could be affected since you’re spanning more material. Many designers stick with 1+6+1 to balance performance and manufacturability.

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Before answering the questions, the first thing to fix is the layer stack. The first rule to apply is that it should be reflectively symmetric about the centre of the board. The present stack is:
1 - sig
2 - plane
3 - sig
4 - plane
5 - sig
6 - plane
7 - plane
8 - sig

It should be:

1 - sig
2 - plane
3 - sig
4 - plane
5 - plane
6 - sig
7 - plane
8 - sig

Being specific you need:
1 - high-speed sig
2 - GND
3 - high-speed sig
4 - GND
5 - Power
6 - low- speed sig
7 - GND
8 - high-speed sig

Q1. Yes you do need L7-L8 HDI because of symmetry.

Q2. Risk of 1+8+1 is that it will cost you more.

Q3. Megtron and I-Speed are both fantastic materials. The question is whether you need them. I have used them in RF projects, but for digital with USB3 running at 10 Gbps, standard materials are fine if you are not using really long traces.

Q4. If that via stack-up is actually possible, it will be very expensive. On an 8-layer board there are far better solutions. The difficulty is that there are quite a number of tradeoffs which make a definitive answer hard to give. What you propose is probably not manufacturable.

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GND should act as the reference for high-speed signals. Will it still serve this purpose effectively if we stack the layers like this?

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Thanks again for the insight. Since my pitch is 0.5 mm, I’m finding it quite challenging to fan out using through-hole vias due to the limited space. I considered the dog-bone method, but with a minimum via diameter of 0.15 mm, it doesn’t seem suitable for 0.5 mm pitch

I then explored HDI techniques, particularly via-in-pad with microvias. From what I’ve seen, mechanical vias are mostly used with dog-bone fanouts, and I haven’t found much information about using mechanical vias directly in pads. I initially tried blind via-in-pad with 0.15 mm mechnical vias, but I’m unsure if that approach is manufacturable or considered standard practice.

I also came across a 1-6-1 stack-up on some manufacturers’ websites, which aligns with what I’ve learned — that FBGA packages are typically fanned out using via-in-pad techniques, while CBGA often uses dog-bone methods. Based on that, I chose to proceed with the via-in-pad technique.

Since I’m interfacing DDR3, I’ve allocated three high-speed layers — two for the data byte lanes and one for control signals.

Would it be considered acceptable or practical to use L1–L5 mechanical blind vias in this case? As this is my first high-speed design and multilayer board, I’d really appreciate your advice on whether that’s a sound approach or if there are more practical via strategies and stack-up options that would improve both manufacturability and signal integrity.

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I agree with Jonathan. The stack-up has to be symmetrical. High Speed signals on Top and Bottom layers and power plane and GND as close as possible to minimize loop inductance.

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The reference plane is the nearest metal (whether it is on the board or off it) in any given direction in 3-D space. But the effective reference plane(s) will be those that are closest to the signal trace. In the image that you give the nearest metal to layer 8 signals is of course layer 7 which is why we defined that this should be a GND plane.

As layers 2 and 4 are also both GND planes, the currents that the signals on layer 8 induce are in the GND plane on layer 7. From this it is immediately obvious that although layers 2, 4 and 7 are all called GND, and are coupled together, they definitely do not have the same currents flowing in the same parts in the same directions. They are different, but linked.

Although we say that the current flows “in” the plane, to be more precise it flows “on” the plane and the penetration depth of the current is usually very small. This means that one side of the plane and the other side of the plane will have different currents flowing! The bottom line is that the energy transfer takes place in the gap between the plane and the signal layers, and the metal on each layer is acting as a waveguide to direct the path.

Since the GND planes are clearly not the same, what happens when the signal transitions from layer 8 to layer 1? After all, both of these are GND plane! Yes, they are GND planes but the signal only references the “nearest metal in every direction” so the current you are causing to flow in the layer 7 GND now needs to flow in the layer 2 GND. How can it get there? It uses the vias to change layer. These vias should be as close as you can possibly get them to the signal via linking layers 1 and 8. Ideally the GND linking via (or better, vias) is right next to the signal via, but life is often not so kind and you may have to put it further away while realising that this is less than ideal but better than none at all.

At this point you are now very grateful that both layers 2 and 7 are GND, because coupling the planes that the displacement currents are flowing in is now trivial. One or more vias next to the signal via solve the problem. What if one of the planes was say VCC? A coupling via becomes a power to GND short. One option is link them through a capacitor. The problem is that the impedance of all decent decoupling capacitors is high at the frequencies that are being induced in the planes by your signals. (Look at an impedance plot for a typical 100nF 0402 part and the inductance of it dominates above 30 MHz or so - but what frequency are your signals - 10x, 100x?)

Let’s also briefly look at what happens for signals on layer 3. Their displacement currents flow on layers 2 and 4. Will this be equally? Only if the spacing between layer 2 to 3 is the same as that between layer 3 to 4, otherwise it is biased one way or the other.

The only layer with a problem is therefore signal layer 6 because it induces currents flowing in layers 7 and 5. Layer 5 is the problem because it is not another GND layer. Fixing this partially is possible by spacing layer 6 much closer to layer 7 than to layer 5 and so you have an engineering compromise … but it’s better than nothing.

With this in mind, what do you want in your stack-up? It is getting to look more like this:

1 - high-speed
thin prepreg
2 - GND
thin prepreg
3 - high-speed
thick core
4 - GND
thin prepreg
5 - Power
thick core
6 - low speed
thin prepreg
7 - GND
thin prepreg
8 - high speed

This is a 2+4+2 stack-up.
The vias are now:
Through vias 1-8
microvia 1-2
microvia 2-3 (or skip vias 1-3)
buried vias 3-6 (may not be necessary)
microvia 6-7 (or skip vias 6-8)
microvia 7-8

When it comes to two layers of microvias, the “safe” route is to stagger them. The denser route is to stack them on top of each other. But this is a question you should address to Sierra Circuits as to which is “better”.

So in answer to the question, can GND on layer 7 serve as a reference to signals on layer 8, the answer is Yes.

Perhaps this also goes some way to answering the other question that was raised.

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