Mark your calendars to join our LIVE Q&A on HDI PCB design and fabrication!
Post your questions in this thread and our experts will reply during this live Q&A which will be hosted on Zoom.
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Notes:
This is not a webinar. There will not be any presentation. We will only answer questions during this session.
How would you optimize the layer stack-up for better SI in an HDI design?
What advice do you have for managing thermal dissipation with densely packed components in a layout?
What’s the smallest trace/space you can do? Does the board become less reliable the smaller you go? For instance 3mil vs 6mil.
Can you assist with choosing the right via structure (stacked vs. staggered) for cost and performance? I hear stacked is not recommended.
Do you have recommendations for reducing the risk of warpage in an HDI board with a large number of layers?
I’m concerned about reliability; what recommendations do you have for increasing the durability of microvias?
Do you have best advice to manage the aspect ratio to avoid fab issues?
Thanks for joining, everyone!
Here’s the recording: