HDI designs can push performance but they also push limits.
From stacked microvias to material selection and layer registration, HDI PCBs come with their own set of challenges.
What’s been the toughest part of working with HDI?
Honestly, via-in-pad on stacked microvias has been a pain. I get why it’s useful for dense routing but convincing the board shop it’s worth the added complexity (and cost!!!) is always a battle. Anyone else dealing with this?
Registration issues drive me nuts haha. When you go for tight RF build even a tiny misalignment between layers can wreck impedance. We’ve had to tweak our designs just to give the fab some wiggle room. Curious how others are handling this.
For me, the toughest part is optimizing the stackup. It’s always a balancing act, trying to meet impedance requirements with thin dielectrics while keeping the layer count in check. Then you have to figure out the best mix of blind, buried, and microvias for routing efficiency. On top of that, material selection can be tricky, you want low Dk and loss but also need good thermal and mechanical performance. It really feels like solving a multi-variable puzzle every time.
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One challenge I don’t see mentioned often in HDI is the lack of standardization across materials, processes, and definitions of what constitutes HDI itself. For instance, a design optimized for miniaturized consumer devices (e.g., smartphones) uses vastly different materials and microvia strategies compared to high-performance computing or automotive boards. This variability forces designers and fabricators into a constant loop of customization, requiring test vehicles, DOE and statistical process control for every unique stackup, it’s a constant cycle of customization.
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Could you expand on this? I understand how thin dielectric requires thin traces, and thin traces can tighten required tolerances or make vias harder. But I don’t see how misalignment affects impedance directly unless you’re doing something like run routing just a strip of ground.