Hello- I’m trying to get an HDI design quoted here and running into some issues with my first-pass design and am not sure what the best way to resolve them is. I’ve been pouring over HDI design guides but am not yet able to fully weigh the design tradeoffs for various ways of achieving an optimal layout for the 0.4mm pitch BGA in my design.
Currently, I have a 2-2-2 stackup with uVias and buried vias as shown.
Based on my board thickness, I am using a uVia with a 6mil hole and 10mil pad.
For the buried via, I have a 6 mil drill and 11 mil pad, which I thought was the minimums for Sierra circuits (I’m getting DFM feedback on the quote that a 12mil pad is the minimum)
Anyway, with there are a few spots in the BGA that I need to stack microvias on buried vias to breakout from layer 6 (bottom layer where the BGA is) to layer 3. The 11mil pad on the buried via results in a ~2.7mil spacing from pad to pad layers 3 and 4 where the buried vias are in 6 or so locations at the center of the BGA. That spacing violates the 3mil capability (3.25 according to DFM feedback). I don’t know the best way to resolve this and am looking for input.
My first thought is this will require adding additional layers and sequential laminations to the stackup so that I can use a stack of laser uVias to get down to the 3rd breakout layer. That would probably mean a 3-2-3 stackup. Is that such a thing? This seems like an expensive approach and am hoping for something simpler.
I see IPC 6012 Class 3 allows smaller annular rings. Is that just an inspection thing, or does it drive different processes in manufacturing? Is there some way that could get me out of this predicament or would it be more expensive than adding additional layers and laminations.
Is stacking uVias on buried vias better/worse/about the same as stacking uVias on uVias in terms of reliability?
When staggering uVias, what is the minimum pitch between holes? I didn’t see that in the capabilities. I saw it was 0.4mm for drills. What about min pitch between a uVia and a buried via?
Sorry for all the questions, but I would appreciate any help in aiding my understanding!
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Adding to my confusion- I just ran the stackup tool again and it still recommends a 6 layer design but lists a 10mil pad for the buried vias in the BGA area:
If that is feasible, then I think I should be all set with my current stackup and design if I reduce the pad to 10 mils as it is on the uVias.
Is the tradeoff lower yields? Higher failure rate?
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I would not expect Class III (high reliability) to allow smaller annular rings. I thought it required wider annular rings, in part because it doesn’t tolerate breakout. The rings should be thick enough that there is a still an extra mil around the hole even if the pad or drill are slightly mispositioned. Class II lets the hole slide a little farther to the edge of the pad.
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Our design engineers will have a look and get back to you. Hang in there! 
[I am not affiliated with Sierra, so trust their official representatives when they get back to you.]
I’m looking at https://www.protoexpress.com/products/rigid-pcb/ and I’m not sure which process you’re planning to use. (Standard/Advanced/Micro), nor which type of drill (laser drill can get slightly smaller).
I think that “process pad” is the copper you have to stay far enough away from, but that is larger than the drill, which in turn is larger than the finished hole.
Unfortunately, the drill won’t go exactly where you planned. The standard process says to leave an extra 12 mils, which works out to 6 on each side of the hole, but then says you’ll only get a 1-mil annular ring. The other 5 mils are to leave room for the drill to “wander”.
You can reduce that extra space if you go with a laser drill or a more advanced process or accept a hole at the edge of the pad with no remaining “ring” outside it.
You might not be able to reduce that extra all the way to the minimum clearance between traces, because the other drill from the next via might wander the wrong direction. (It isn’t really all in the drill; some is the board itself shrinking differently. That helps a little, because nearby vias will be more likely to wander in the same direction.)
And when you asked about staggering vias vs stacking them … it might matter whether the bottom (buried) via is another microvia (layers 2-3) vs the symmetric originally through-hole via between layers 3-4.
You also might be able to save some money if there is a layer of vias that you don’t need. For example, if you don’t actually ever go from layer 4 to layer 5 without being able to drill all the way through, then they can skip carefully positioning the board for that set of vias.
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It makes sense logically that class III would require larger pads and such if its goal is higher reliability. I think I was getting confused by the text below in the explanations. They are referring to the acceptable measured annular ring of 1 or 2 mils after drill wander, not the designed pad size as I initially thought. I figured maybe class III required some special more precise drill method.
Thanks for the help!
@rmcdaniel our designers say they need to ask you a bunch of questions before they can reply so expect a call from them today.
Would like our CAM manager to confirm but here is what I can say:
- The 6mil drill & 11 mil pad is fine for the buried vias. This is a sub so it’s drilled then imaged with the pad aligned to the drill so registration is tight. Be different if it was an internal pad that’s imaged then drilled and need a bit more room for registration
- The 2.7mil pad to pad spacing is OK
- You can stack a laser vias on top of the blind vias but the blinds need to be filled and capped. There is no real difference between stacking on a filled/capped blind and another laser via.
- It’s best to stary with the .4mm spacing for everything if possible. Can get tighter but it takes a more advanced/limited build strategy.
- In regards to the Class 3 question, might be looking at the minimum remaining annular ring requirement that Class 2 doesn’t have.
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Our CAM manager Gopal confirms this is correct.
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Thank you all for the help (and Greg for the call yesterday). I was able to reduce a lamination step by moving the buried via to 2-5 and get the via sizing dialed in so that it is passing the DFM screenings and can be quoted.
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Cool to hear. Thanks for the update!
Wait … are you saying that “where the pads go” can be adjusted even after you see where the drill went, so long as the pad is on (currently) an outside layer?
based on my experices, I have done a 0.5mm pitch layout but not a 0.4mm pitch design. 3mil trace, 3 mil space.
It is generally not recommended to stack microvias on top of buried vias.
6 mil laser drill on 10mil pad is likely not practical. 5 mil laser drill on 10 mil pad is more realistic but aspect ratio might drive thinner dielectric thickness requirements.
As far as hole to hole clearance for same net staggered microvias (not plated closed), you do not want any hole overlap so I think you can likely get by with a few mils of clearance hole edge to hole edge. When doing stacked microvias, those will need to be plated closed. I doubt that your design will want different net vias on less than a 0.4mm pitch.
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