Webinar: Using HDI to Improve Signal Integrity and Power Integrity Performance

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Three concerns: 2 SI and 1 PI.

We have a 1400+ Ball BGA 0.8mm pitch so our stackup has 8 HDI prepreg layers on the top and 8 on the bottom with power layers in between. 0.112" thick. 28Gbps SERDES.

  1. 1st concern is mfg. tolerances and possible increased loss with traces getting plating with 8 prepreg layers on top of each other for constructing precision multilayer via and trace structures at 28G. I’ve heard that the plating that covers the traces will mess up the VLP copper increasing loss and maintaining impedance tolerance may be difficult to achieve. Is the mfg. variability known and is this a heavy lift for our US board folks?

  2. Breakout - There are effectively only two available signal layers for us - L3 and L5. L7 has a dense processor bus on it. The SERDES are in every column and are 6 deep into the BGA array so I am thinking that there are not enough routing layers available to do this. 1 more would probably do it. I’ve looked for routing/breakout guidelines for HS SERDES 0.8mm pitch microvia via structures (we are staggering with foldback) and cannot find any.

  3. PI Concern. Because the power layers are in the middle of the board I am concerned with both increased IR drop through staggered microvias (as long as 0.130") going from L8 to L1 and increased inductance for higher freq. supplies - a lot of caps are bottom layer so there are two sets of staggered microvias to get to the top BGA. Don’t know if there is room in a 0.8mm pin field for big through or core vias or maybe a blind from L1 to L8 would work with a core via through the power layers - but this eats up copper on the planes - Bottom of the board is RF so I have to be very careful about what to do there.

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VLP has to do with limiting the dendrite structure on the bonding side of the foil. Plating on the traces has no effect on it as it’s sealed up against the dielectric during lamination. No increased loss and trace tolerances for controlled impedance are easy enough to control. Also inner layers typically use just the base copper and there is no additional plating.

I asked Happy and he said, “8+2+8 is PUSHING what you can reliably fabricate. I suggest that you use some of the techniques in my Webinar 2 (New HDI BGA Breakouts and Routing Strategies | Sierra Circuits ) to reduce the breakout BU layers or switch to VeCS HDI construction as it only requires one lamination for the 8+2+8 and you can ‘shield’ the HF traces.”

For a good guide to this try SERDES implementaion guide - Google Search

And don’t be hesitant to add the layers if you need them.

Thank you Steve for you response. I guess that I am confused. When I look at our stackup that has the 8 prepreg layers on top of each other it looks like the copper is a little thicker and I though that this was due to plating when the microvia holes are plated. If this is so doesn’t that extra buildup of copper represent uncontrolled roughness and therefore more subject to loss? Best Regards, Ned

Thanks Very Much for Getting Back to Me Lucy. Thank Happy also! I thought this, as it is greater than what I see in the technology roadmaps from various PCB fabs. I will take a look at the Webinar. I notice that the link to the EBook is no longer valid. Do you have a link for this book. Do you think Happy will be available for one or two followup questions one or two days afterward? I am in a work crunch and my response time is not so good at the moment. I can tell you that when I use the clearances that I am given by our ECAD folks that it is very difficult if not impossible to create controlled impedance HS SERDES breakouts, and still be able to have routing channels to route everything out, not sure what to do there. Thx, Ned

Thank You Al, I will check this out! Ned

You can download Happy’s HDI Handbook here: HDI Handbook :: I-Connect007

I’ll ask our design engineers for the rest.

I’m on a call with Happy right now and he says, “This is the reason why a 8+2+8 stack-up will be very difficult to build. I would do a 3+2+3 to breakout the entire BGA in two routing layers. See the techniques mentioned in the BGA webinar.”

He says you can also email him.

You might be seeing the flash/panel plate that’s needed for both the wrap requirement and to ensure good power distribution in the microvias during plating. Electrolytic copper plating by its self is pretty smooth so any additional plating doesn’t increase roughness. There is actually a leveling component in the plating chemistry that helps provide a smooth surface.

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