I’m currently trying to design coplanar waveguide (CPWG) structures and PCB trace antenna design, and I have a couple of technical questions I’d appreciate input on.
To minimize parasitic capacitance—given the thin dielectric between Layer 1 (CPWG) and Layer 2—I removed a portion of the ground plane on Layer 2 adjacent to the CPWG trace. I also cleared the signal plane on Layer 3 directly beneath the removed Layer 2 region. This forces Layer 4 to act as the primary return path, increasing the effective ground-to-signal height (H) and reducing capacitive coupling
Question 1: CPWG Height Reference
When calculating the dielectric height (H) between the signal and ground for CPWG impedance, should the copper thickness of Layer 3 be included in this value, or is H purely the dielectric thickness?
Question 2: Trace Antenna Ground Clearance
For the trace antenna, I understand that no ground plane should exist directly beneath the antenna. Does this mean I need to maintain a ground/power plane keep-out zone across all layers beneath the antenna, including internal layers like Layer 5, which in my case is a power plane?
I’d appreciate any clarification or design guidance you can share. Thanks in advance
I think the height is included/ignored at your convenience.
Strictly speaking, the inner copper layers are not included because they don’t exist because they have been etched away. But since that makes this section of the board a little thinner, some of the prepreg (the epoxy or otherwise liquid portion) will flow in from nearby, and build the thickness back up, while reducing it slightly for the rest of the board. Alas, the epoxy has slightly different electrical characteristics than the glass weave, so now you need to use a slightly different Dk, etc.
The normal way of handling this is to effectively say “The copper layer is pretty thin compared to the entire thickness of the board, so the deviations will be tiny. Perfection doesn’t exist, and this will be close enough.”
Even before quoting, some web forms will ask what percentage of copper is still covering each layer. Ideally, the board house will use that to calculate final pressout thickness and a more accurate/precise Dk (for their process with this copper coverage) than is advertised by the FR4 manufacturer in the generic case.
If you end up losing ~ 6 mils of copper out of 60+ for the entire board thickness, and you gain most of that back, the extra epoxy that flowed in is still less than 10% of the thickness, and the different Dk values weren’t hugely different to begin with, so your final effective Dk may be off by 1 part in 1000. That should matter less than solder mask, and the board house can even make some corrections based on their past experience. If that isn’t tight enough control, you probably shouldn’t trust any advice that isn’t in a binding contract with sample items that you measured and verified yourself.
“Need” is probably too strong, but the sample designs assume you will do that. Sometimes they make additional assumptions about how close the enclosing case will be, or whether people will hold it in their hands. And sometimes these assumptions are wrong; that is one reason to leave room for a tuning circuit that can adjust things once you get a physical prototype for testing.