Coplanar waveguide without a parallel ground signal

I don’t know much about this, so I’m seeking advice. Can we generate a coplanar waveguide structure without a ground signal parallel to it, as recommended in the datasheet of the NEO-M9N GPS? If so, can we add ground vias instead? What clearance should we consider between the ground via and signal?

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I asked our design team to get back to you.

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Create the stackup with 50 ohm Coplanar waveguide so it will gives you trace width and clearance from GND for RF lines. You need to exactly maintain same value and stich with GND vias on the design.

You can use our online stackup designer to create stackup.
https://www.protoexpress.com/tools/pcb-stackup-designer/

Regarding GND reference, Please see recommendation from datasheet and need to follow the same.

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Thank you for your response.I designed a coplanar waveguide (CPWG) structure for an RF design using the Broadcom AppCAD tool. The stack-up uses FR4 material, with the 1st layer as Signal, the 2nd and 3rd layers as Ground, and the 4th layer as Signal. The dielectric thickness between the first and second layers is 0.144 mm.

I’m confused about arranging components when there is a parallel ground signal. The signal width is 0.25 mm, and the clearance between the signal and ground is 0.2 mm. As a beginner, I understand the importance of having a parallel ground signal to the RF signal. However, without creating a stub, I find it challenging to arrange this. Can I use a ground pour zone on the first layer along with a via fence to achieve the CPWG structure instead of a parallel ground signal?

For RF line, we usually needs to follow 50ohm CPW that means GND pour should be there on the external layer (we should maintain exact trace width for RF line and spacing (between RF line & GND on external layer)).

Regarding parallel GND, We need to follow as per datasheet recommendation.

You can refer blog from our website.

https://www.protoexpress.com/blog/antenna-integration-rf-design-guidelines-for-5g-pcbs/

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This comment is not really an answer to the question originally set, but is a remark to help understand what might appear as a bit of an anomaly in the “Figure 39” image.

Most coplanar structures (this included) expect there to be a GND plane under the traces carrying the RF, but for the moment, disregard that GND. Only consider the distance between the signal trace and the GND on either side. This distance can be calculated using field solvers for a given stackup. As such, it is treated as a 2-D structure - a slice passing vertically through the PCB at 90 degrees to the signal trace.

The solver will give you a separation distance between signal and then GND on either side, but a quick look at the connector marked J2 in Figure 39 shows that at this point the separation is considerably larger. It at first looks like a mistake, but this is actually quite correct.

Without this wider than expected gap under J2, the point in the middle of J2 where the signal enters the board would look like a significantly lower impedance than the 50 Ohms it wants to see, and so would reflect some of the RF back. This is because the centre terminal of J2 has to be equally close to the GND that surrounds it through an angle of nearly 360 degrees. This is not true for a point in the middle of the RF trace where the GND is closest at 90 degrees, but as you turn towards 180 degree or 0 degrees the distance to GND in those directions increases. It now becomes clear that by increasing the clearance from the centre pin, this compensates for what would be an impedance mismatch at the point where the RF signal passes from the connector and into the PCB trace. Exactly how much wider the clearance needs to be depends on more factors (especially the height of the signal above the plane below), but a very good approximation can be made as has been done here - to make the clearance circle big enough to just touch the four GND pins/pads of this connector.

While the connector has been handled properly, it follows that the other end of the trace where the signal goes into the RF module may be not quite perfect, as a wider clearance might be expected here. It is to be hoped that the module manufacturer knew the physical constraints present on the board that their product would be mounted on, and they compensated for this inside their module. We have to trust them in this that their PCB design here is optimal. At least, the reason why the coplanar separation under J2 is different from the separation along the RF trace has been explained.

If your plan is to replace the GND pours on the same layer as the signal with vias, make sure that under J2 the vias are as far out as the copper shown in Figure 39, don’t bring them closer or move them further out.

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What do you mean by not having “a ground signal parallel to it”?

Do you mean that the area around it would have the copper etched away? (Then what is the co-planar part of the CPWG?)

Do you mean that a copper plane (or copper pour) would be used instead of just a trace? (Normally fine, though you might need slightly greater separation or narrower signal trace to maintain impedance?) Via fencing from that plane/pour should work at least as well as from a narrower trace. (Unless you take advantage of the pour to move the vias farther away or space them differently?)

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To clarify, when I mentioned “not having a ground signal parallel to it,” I was referring to my decision to use a copper pour (plane) on the same layer as the RF signal, instead of running a dedicated ground trace alongside it. As a beginner, I wasn’t initially aware of the ground pour technique, so I had been using ground traces, which made it challenging to avoid vias in the RF design.

Now that I’ve finalized the design, I’ve switched to using a ground pour and incorporated via fencing. Thanks for your reply and for taking the time to help

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