I’m a beginner in PCB design, and I’ve been working on a coplanar waveguide (CPW) structure for an RF signal on my PCB. Here are the details of my design:
Signal Trace Width: 1 mm
Clearance for 50 Ohm Impedance Matching: 0.2 mm
Board Length:50 mm
I’m currently at the stage of adding via fencing to this CPW structure and need some advice. Specifically, how much clearance should I maintain between the vias and the edge of the RF signal trace to ensure effective shielding and optimal performance?
For the clearance between the vias and the edge of your signal trace, a general rule of thumb is to keep the vias as close as possible to the trace edge without violating your PCB manufacturer’s design rules. Typically, this is around 2-3 times the width of the clearance between the signal trace and the ground plane (in your case, 0.2 mm), so you might consider a 0.4-0.6 mm clearance to start with.
And I can add the below points,
For effective shielding, via spacing should generally be less than 1/4 to 1/10 of the wavelength of your highest operating frequency. This helps block unwanted coupling and leakage.
If you’re working with high frequencies, check that the via placement doesn’t create unwanted resonance or affect the return current paths.
Ensure your design complies with your shop’s capabilities for via-to-trace spacing and via drill sizes. I don’t know what Sierra’s are.
You might want to share your operating frequency too.
Okay, if I understand correctly (I’m going to use Imperial units here), you have a trace that’s 40 mils wide (I’m also going to round a teeny bit), and it has a gap between it and a ground pour on the same layer (CPW) of 8 mils, but you didn’t give some details like what laminate you’re using, so I’m going to make a couple assumptions that are mainstream and seem to fit this. Let’s assume we have a dielectric constant of 4.3, and an overall thickness of 31.5mils.
When I press the magic button on my computer, it tells me I hit 49.8059 ohms. Rounding that down, I’d say 49.8 ohms is a darn good first pass. So when placing any vias for EMI reasons you would definitely not want the edge of the vias annular ring to come any closer than eight mils, so the hole would be (let’s say) at least 16 mils away. In practice this is still a little close as it may lead to manufacturing issues.
That’s why we call out 2x and 3x clearances for pours and vias and other copper features. The via is close enough to do it’s job, far enough not to get in the way. Having any copper closer will change the impedance at that point slightly, and will also capacitively load the trace increasing the loss. Sounds like you’ve narrowed in on your target pretty well.
