I’m investigating a conducted emissions issue on a 4-layer PCB and would like to sanity-check my understanding of the return-current path.
Stackup:
L1 (Top): Signals + stitched GND pour (0.065 mm to L2)
L2: Solid GND plane
L3: Routed power rails (1.2 mm to L2)
L4 (Bottom): Signals + stitched GND pour (0.065 mm to L3)
Because the routed power on L3 is much closer to the L4 ground pour than to the solid L2 ground plane, my understanding is that the high-frequency fields will couple more strongly to the L4 pour.
The challenge is that L4 isn’t a continuous plane, it also carries signal routing, so the ground pour is interrupted in several places. When the return path encounters these gaps, it has to detour through the pour or transition to L2 via stitching vias.
Could these interruptions in the closely coupled return path contribute significantly to conducted emissions?
Would it be better to remove the L4 ground pour in those areas and rely on the solid L2 plane instead, or is this fundamentally a stack-up issue that should be solved by rearranging the layers?
Return path interuptions depend on the signals and what the return path looks like. Keep in mind that the signals on L4 will likely path on L4 GND pour and layer 3 PWR instead of layer 2.
The trick with L3 as a return path for layer 4 is whether the L3 PWR copper creates a proper return path and whether the layer 3 PWR voltages are related to the signal looking for a return path. If the voltages on layer 3 are not feeding the signal circuit, then the return path will be much more convoluted and harder to analyze. You might need to add caps between PWR copper to help bridge return path signals…but this is may not a perfect solution depending on many variables.
Is is hard to suggest a potential solution but one idea if it can be implemented would be to have both L2 and L3 as GND layers and run the PWR along with signals on layers 1 and 4. This would allow more ideal return paths assuming L1 and L4 can supply PWRs to circuits.
Some peers might suggest removing signal GND copper but I personally prefer to keep signal layer copper in most cases.
You can also consider swapping L3 and L4 but managing impedance control will still be an issue depending on dielectric thicknesses between layers. You might not think that impedance control is required but even if it is not crtical, impedance calculations can help you decide how signals will be treated while traveling across the board. If you are worrying about return paths, then you also should be reviewing impedances of those same signals…even if you do not require a specific impedance result.
One thing I’d check is where the return current is forced to transition between L4 and L2. The issue isn’t simply that L4 has gaps. it’s whether those gaps force the return current to make a large detour before it finds a stitching via. That increases loop inductance and can convert part of the return path into a source of common-mode noise.
If the L4 pour is retained, try to place stitching vias close to every significant interruption so the return current has a short transition path to the solid L2 plane. If that’s not practical throughout the board, then the limitation is likely the stack-up rather than the ground pour itself.