I’m working on a six-layer PCB with the following stackup:
L1: Top (signals)
L2: GND
L3: Signal
L4: PWR
L5: GND
L6: Bottom (signals)
Some high-speed signals (USB3 differential pairs and a 4-bit SDIO bus) had to be routed on L3 due to space constraints. To maintain return paths, I’ve added stitching vias near signal vias when moving between layers.
My question is: since L2 and L4 are both solid reference planes, do I also need stitching capacitors at the start and end of these L3 traces? Or will the return current naturally prefer L2 as the lower-impedance path, making the capacitors unnecessary?
In general, return paths tend to lean towards the physically closer plane. So while you are defining the impedance stackup, keep that in mind. Generally GND layers are better for return path than PWR layers. If you are using PWR layer, be sure that the PWR is correct for the signals. In other words, avoid referencing PWR copper that is not for that circuit.
If the high speed signals are starting on top layer, you should not strictly need stitching vias since top and L3 layers are sharing the same L2 reference layer.
Routing high-speed signals on L3 is fine, but the key is how L4 (the power plane) is used. If that plane carries a sensitive analog supply, you risk coupling noise into it from your high-speed traces.
The spacing between planes also matters. If L2–L3 spacing is much smaller than L3–L4, then L2 will naturally act as the main reference plane. But if L3 is very close to L4, the return current may couple more strongly to the power plane instead. In that case, you need to think carefully about how the current returns, because a PWR plane can only return high-frequency currents if it’s properly tied to ground through decoupling capacitors.
The important point is that displacement current flows in whatever adjacent plane exists, regardless of whether it’s labeled GND or PWR. As a rule of thumb, it’s best to keep a ground plane directly adjacent to every signal or power layer, and keep that spacing tight. This minimizes ambiguity about the return path and reduces EMI risk.
At present there are already two very good replies from @timothy.phillips and @jerrysaitter but there are a few more things that are worth giving a little thought to. The first of these is that you need the core that separates L3 and L4 to be the thickest core you can manage within the board constraints. The separation of these to layers is vital.
The second concern is copper weight balancing. L3 is a signal layer, L4 is a plane, so you are going to need to add copper to all of L3 that isn’t signal traces to get the balance close. This extra copper should be connected to GND because that’s what L2 is.
The third concern is impedance. The USB3 line impedances will be dominated by L2 because of proximity, but L4 will also play a part and cannot be neglected. Also the GND pour (in concern 2) will also have an impact but whether your impedance calculator can cope with this is another matter. The PCB manufacturer can probably help out if your own tools cannot.
The fourth concern is the question of decoupling capacitors. The biggest problem here is that of the parasitics of the capacitor and the unavoidable impedance of the vias and tracks that connect to it. These capacitors are only likely to be of any use if they are C0G (or NP0), but even then you may find that taking them off makes very little difference because the parasitic effects dominate. Better to have the pads and try than not. You need the physically smallest capacitors and the vias to the power planes must be under the capacitor and as close as possible to maximise the inductive coupling between them.
The fifth concern was whether the USB3 signals might put noise on the power plane. This is likely to be a very minor effect because if you have good separation between L3 and L4, the fact that USB3 is differential means that the influence of the equal but opposite USB signals seen by the plane largely cancel each other out. Unless you have ultra high precision analogue circuits this is not likely to be a problem.
If it is possible it is always better eliminate VIAS. So the best option is always to route high data rate signals in the same layer as the IC is located. If this is not possible the opposite layer (top or bottom) is the second best option because the VIAS don´t introduce any kind of stub. If you have to use layer 3, the best scenario is L3 as close as possible to L2 and significantly separate from L4. Some manufacturers use similar distances between layer 2 and layer 3, and layer 3 and layer 4. In this case the impedance the signal sees is the impedance between layer 3 a PWR plane + impedance between layer 4 and layer 5. The distance between PWR and GND the shorter the better (to minimize loop inductance).
Keep in mind any capacitor between PWR and GND doesn´t do a good job at high frequencies so this is not the way how the return current goes to the GND plane.
You don’t always need stitching capacitors on L3 traces. If L2 is much closer to L3 than L4, return current will naturally flow in L2 and extra caps won’t help. Caps only matter when the power plane (L4) is so close that it acts as the main return — in that case, you’d need decoupling between L4 and ground to provide a low-impedance path. If you do add them, keep the caps very small (0402/0201), with vias right at the pads to minimize loop inductance. Otherwise, good layer spacing and stitching vias near signal transitions usually solve the problem.
Slightly off-topic, but your stackup looks mechanically unbalanced. Are you planning to run this board through reflow? With asymmetrical copper and dielectric distribution, there’s a higher risk of warpage, which can cause assembly problems, especially with BGAs.
If the layout is done carefully, there should minimal concerns about warping. This type of stackup is used on many products. Layout needs to add as much copper to the signal layers as practical in order to minimize copper % between the top and bottom stackup halves.
Dielectrics should be symetrical betwen the stackup top half and bottom half.
Yes, this board will go through reflow with some fine-pitch BGAs. My main focus so far has been on signal integrity, that’s why I placed GND on L2 for the top-layer signals and used L4 for power distribution. I hadn’t fully considered the mechanical balance, but I’ll check if I can add copper fills on the inner signal layers or any unused areas to balance the copper distribution and keep the dielectric thickness symmetrical to minimize warpage risk.
One thing to consider, if you have flexibility to tweak the stackup, it’s generally best to keep a ground plane adjacent to every signal layer. For example, you could mirror L2/L5 as grounds and use L3/L4 as signal layers. That way return paths are unambiguous, and you also get a more mechanically balanced stack. Of course, this only works if your routing constraints allow it.
You’re right, with only one defined inner signal layer (L3) in the original stackup, my suggestion was more about a possible alternative stackup rather than the exact one shown. The idea was: if the design can be adjusted, pushing both L3 and L4 to signals while keeping L2/L5 as grounds would give cleaner return paths and better balance. I should have phrased it more clearly as an option rather than a direct fix for the given stack.