Noise concerns with SPI bus routed through vias

I’m curious about the impact of routing high-speed signals, such as an SPI bus clocked at 4MHz, through PCB vias.

I’ve observed significant noise (±350mV) on my SPI bus signals, which operate at 3.3V levels. Despite the relatively short signal traces (about 6cm), they traverse approximately 5 vias each on their path. The board is limited to 2 layers, necessitating multiple vias on these lines.

I’m interested to know the potential noise introduced on a signal trace when changing layers through a via.

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There is no absolute value for that, and I doubt if it would be easy to try to calculate. Your question brings up some other questions though. For example is the bottom layer setup to be a ground plane? How close are other signal traces? Overall, what single-ended controlled impedance and differential pairs to you have? 4 MHz is not very fast, but the real speed concern is the rise and fall times, which could require as much as 30 MHz of bandwidth… That’s still pretty slow, so I wouldn’t expect much distortion due to a skew in impedance. Lend a copy of your files if you continue to have problems.


350mV is quite substantial for a 3.3V bus. However, vias themselves typically add only a few nanohenries (nH) of inductance, which is negligible. If the capacitance on either end of the via is under 100pF, and considering a trace of such short length would have a resistance under 0.1Ω, any potential RLC resonator effect would be well beyond the operating frequency of 4MHz, making it unlikely to cause issues.

Transmission line effects generally become noticeable at much higher frequencies, typically around 50MHz, so at 4MHz, these effects should not be a concern.

The primary issues often encountered in two-layer board designs involve common mode noise due to improper grounding practices, such as daisy chaining grounds. Therefore, the first step in troubleshooting should involve examining the grounding system to ensure that currents are not generating common mode noise through interconnected traces.

Another potential problem area could be related to grounding and the placement of the oscilloscope ground connection.


The problem isn’t necessarily the SPI clock frequency being too high (4 MHz). Even if the frequency were much lower, such as 0.1 Hz, the signal edges would still exhibit ringing because it’s the edge rate that determines the bandwidth requirement. Microcontroller IO pins are typically robust enough to drive moderate capacitive loads. For instance, according to the STM32F207 datasheet, they can handle a 30pF load with a 4ns rise time or a 10pF load with a 2.5ns rise time, sufficient to support signals up to 100-120MHz.
If your MCU doesn’t allow you to adjust pin drive strength, you can mitigate the issue by adding series terminating resistors (e.g., 33 ohms) at the device driving the pins. This approach reduces edge rates, resulting in lower bandwidth requirements and less ringing. A 4MHz SPI signal traveling 5cm shouldn’t pose an issue, but it’s important to verify the required rise/fall times for your specific chips.
Additionally, keep in mind that your oscilloscope may indicate ringing in signals due to its bandwidth limit (e.g., 100MHz). Signal edges that exceed this bandwidth can appear to exhibit ringing on the scope.

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