Ask Me Anything with Ben Dannan

Ben Dannan will answer your questions on signal integrity and power integrity for defense and space. Start posting now!

I’ve read that Staggered Microvias have worse signal integrity performance than Stacked Microvias, but they are less expensive to fabricate. Have you seen any literature that describes a method for obtaining the best SI performance from Stacked Microvias?

Do you have particular rules of thumb you follow or practices you avoid for good SI/PI? Not just for defense and space, for electronics designs in general.

What are your go-to best practices to reduce power supply and noise in complex designs?

I am working on improving SI but I have some misunderstanding in handling high frequency signals. Resistance and inductance increases with high frequency signals, so I try to take care of that while routing my high speed signals. But while I am referring some documents, they always mentioning faster rise time. Why are they mentioning rise time instead of using high frequency? Do the circuits have different effects on faster rise times? Looking forward to the answer.

Does the implementation of massive MIMO technology in 5G impact PCB design for signal integrity?

How do you handle simultaneous switching noise (SSN) in complex designs with multiple high-speed channels?

How do vias affect the signal integrity of differential pairs, and what measures are taken to ensure balanced impedance in these scenarios?

What are the key differences in routing rules between DDR4 and DDR3?

How do you use S-parameter analysis in RF PCB designs to address signal integrity issues, especially in complex systems?

How does the design of RF filters impact signal integrity, and what considerations are crucial for achieving effective filtering without degrading the signal?

The simpliest approach, is to minimize your Q in your PDN design. A simple rule would be to keep your Q < 2. We want to have a flat impedance in our PDN. If there is Q there is potential for ringing (or oscillation). Our PDN needs to deliver clean power not become an oscillator (which is where you have high-Q).

The biggest difference with DDR3 to DDR4 is the speed increase. So crosstalk becomes a bigger concern. This means for DDR4 routing of these signals needs to be on segregated layers from other sensitive signals. The same impedance matching principals still apply based on the memory controller and memory device you’re using for the channel.

Based on the context of this question, I would assume the concern is around crosstalk, and more specifically geared towards a parallel bus such as DDR4?

If that is true, I would set the spacing of these signals to ensure a minimum isolation. This can be calculated or modeled using EM field solvers.

The ultimate sign-off for these designs is the time domain simulations with EM models of these routed nets and assessing the crosstalk impact on your victim eyes.

Good question. I do not know the answer here. But I would guess that it certainly has an impact.

This is a very broad question, where answer ultimately depends on what is at each end of the channel and the type of RF filter that is being used. However, it is worth mentioning that the typical PCB channel is a low pass filter. This means all of the high-frequency edge content is usually attenuated by the PCB channel. This is one reason why CTLE is used at the transmitter for certain devices, which allows amplification of the higher-frequency signal content before the channel attenuation.

Yes I do.

For power integrity I manage the Q in my PDN design. We do not want sharp Q. We want to have a flat impedance that is matched to our load (e.g, ASIC or FPGA). This is done by using a good EM solution.

For signal integrity, it depends on signal speed in question. For higher speed signals (> 10 Gbps) copper roughness becomes very important to model correctly with your channel loss. I find the most common issues is lack of adequate signal return vias.

These are some basic rules I always follow. There are lots more of course.

This is true. The reason for staggered vias is reliability during temperature changes on the PCB.

I typically model these structures using a field solver to optimize my signal feeds on each layer and the anti-pad to achieve a desired return loss. There are lots of good SI books that touch on these subjects, start with High-Speed Digital Design by Hall and Heck.

S-parameters reflect a model of the channel. Regardless of whether this is an RF PCB or digital PCB, for signal integrity analysis, I always extract a model of the desired signals, which generates (typically) an S-parameter. From there usually it is best to analyze the return loss and insertion loss to identify any possible discontinuities that may impact the signals on this channel. Next, I will do a TDR analysis of this S-parameter to assess the impedance and inductive and capacitive discontinuities on this channel. Lastly, I do analysis in the time domain with IBIS models and these S-parameters to assess the overall signal performance at each end of the channel. It is assumed that the channel compliance points are understood for these signals.

Vias and the surrounding anti-pads add significant inductance and capacitance to the channel. This can lead to significant reflections in the channel. For differential pairs, optimization can be done to model your via transitions in a 3D field solver. In this instance you would model and optimize your signal feeds on each layer, anti-pads, and via structures.